[board] bringup basic T536

board/CMakeLists.txt

@@ -60,4 +60,8 @@ endif()
 
 if(CONFIG_BOARD_AVAOTA-86BOX)
     add_subdirectory(avaota-86box)
+endif()
+
+if(CONFIG_BOARD_TLT536-EVM)
+    add_subdirectory(tlt536-evm)
 endif()

board/tlt536-evm/CMakeLists.txt

@@ -0,0 +1,8 @@
+set(APP_COMMON_SOURCE 
+    ${CMAKE_CURRENT_SOURCE_DIR}/start.S 
+    ${CMAKE_CURRENT_SOURCE_DIR}/board.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/eabi_compat.c
+    ${CMAKE_CURRENT_SOURCE_DIR}/head.c
+)
+
+add_subdirectory(hello_world)

board/tlt536-evm/README.md

@@ -0,0 +1,6 @@
+# TLT536-EVM
+
+The TLT536-EVM is an industrial evaluation board based on the Allwinner T536MX-CEN2/T536MX-CXX four-core ARM Cortex-A55 + Xuantie E907 RISC-V heterogeneous multi-core processor design, with the ARM Cortex-A55 core clocked up to 1.6GHz. The evaluation board consists of a core board and an evaluation baseboard. All components on the core board, including the CPU, ROM, RAM, power supply, crystal oscillator, and others, are based on industrial-grade solutions.
+The core board undergoes professional PCB layout and high/low temperature testing to ensure stability and reliability. It supports optional shielding and can meet various industrial application environment requirements.
+The evaluation board is equipped with a rich set of interface resources, including 13 UART ports (6 RS485, 2 RS232, 4 TTL UART, 1 Debug UART), 4 CAN-FD ports, 4 Ethernet ports, 3 USB2.0 ports, and Local Bus interfaces. It also provides HDMI OUT, LVDS LCD, MIPI LCD, HP OUT/MIC IN, and other audio and video multimedia interfaces. The board integrates a 2TOPS NPU, 8M@30fps ISP, and supports 4K@25fps H.264 video encoding.
+The evaluation board features an onboard WiFi/Bluetooth dual-module and supports optional 4G/5G modules, NVMe solid-state drives, PLP power loss protection modules, and more. It can also be configured with a protective enclosure for direct use in industrial environments, allowing users to quickly evaluate product solutions and conduct technical research.

board/tlt536-evm/board.c

@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <types.h>
+
+#include <log.h>
+
+#include <common.h>
+
+#include <reg-ncat.h>
+#include <sys-clk.h>
+
+#include <mmu.h>
+
+#include <mmc/sys-sdhci.h>
+
+#include <sys-dram.h>
+#include <sys-gpio.h>
+#include <sys-i2c.h>
+#include <sys-sdcard.h>
+#include <sys-sid.h>
+#include <sys-spi.h>
+#include <sys-uart.h>
+
+sunxi_serial_t uart_dbg = {
+        .base = SUNXI_UART0_BASE,
+        .id = 0,
+        .baud_rate = UART_BAUDRATE_115200,
+        .dlen = UART_DLEN_8,
+        .stop = UART_STOP_BIT_0,
+        .parity = UART_PARITY_NO,
+        .gpio_pin = {
+                .gpio_tx = {GPIO_PIN(GPIO_PORTF, 2), GPIO_PERIPH_MUX3},
+                .gpio_rx = {GPIO_PIN(GPIO_PORTF, 4), GPIO_PERIPH_MUX3},
+        },
+        .uart_clk = {
+                .gate_reg_base = SUNXI_CCU_BASE + UART0_BGR_REG,
+                .gate_reg_offset = SERIAL_DEFAULT_CLK_GATE_OFFSET(0),
+                .rst_reg_base = SUNXI_CCU_BASE + UART0_BGR_REG,
+                .rst_reg_offset = SERIAL_DEFAULT_CLK_RST_OFFSET(0),
+                .parent_clk = SERIAL_DEFAULT_PARENT_CLK,
+        },
+};
+
+void neon_enable(void) {
+    /* set NSACR, both Secure and Non-secure access are allowed to NEON */
+    asm volatile("MRC p15, 0, r0, c1, c1, 2");
+    asm volatile("ORR r0, r0, #(0x3<<10) @ enable fpu/neon");
+    asm volatile("MCR p15, 0, r0, c1, c1, 2");
+    /* Set the CPACR for access to CP10 and CP11*/
+    asm volatile("LDR r0, =0xF00000");
+    asm volatile("MCR p15, 0, r0, c1, c0, 2");
+    /* Set the FPEXC EN bit to enable the FPU */
+    asm volatile("MOV r3, #0x40000000");
+    /*@VMSR FPEXC, r3*/
+    asm volatile("MCR p10, 7, r3, c8, c0, 0");
+}
+
+void clean_syterkit_data(void) {
+    /* Disable MMU, data cache, instruction cache, interrupts */
+    arm32_mmu_disable();
+    printk_info("disable mmu ok...\n");
+    arm32_dcache_disable();
+    printk_info("disable dcache ok...\n");
+    arm32_icache_disable();
+    printk_info("disable icache ok...\n");
+    arm32_interrupt_disable();
+    printk_info("free interrupt ok...\n");
+}
+
+void show_chip() {
+    uint32_t chip_sid[4];
+    chip_sid[0] = read32(SUNXI_SID_SRAM_BASE + 0x0);
+    chip_sid[1] = read32(SUNXI_SID_SRAM_BASE + 0x4);
+    chip_sid[2] = read32(SUNXI_SID_SRAM_BASE + 0x8);
+    chip_sid[3] = read32(SUNXI_SID_SRAM_BASE + 0xc);
+
+    printk_info("Chip SID = %08x%08x%08x%08x\n", chip_sid[0], chip_sid[1], chip_sid[2], chip_sid[3]);
+
+    uint32_t chip_markid_sid = chip_sid[0] & 0xffff;
+
+    switch (chip_markid_sid) {
+        case 0x5f00:
+            printk_info("Chip type = A733MX-N3X");
+            break;
+        default:
+            printk_info("Chip type = UNKNOW");
+            break;
+    }
+
+    setbits_le32(SUNXI_SYSCTRL_BASE + 0x24, BIT(15));
+    uint32_t version = (read32(SUNXI_SYSCTRL_BASE + 0x24) & 0xFFFF0007) >> 16;
+    printk(LOG_LEVEL_MUTE, " Chip Version = 0x%04x \n", version);
+}

board/tlt536-evm/eabi_compat.c

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+void abort(void) {
+    while (1)
+        ;
+}
+
+int raise(int signum) {
+    return 0;
+}
+
+/* Dummy function to avoid linker complaints */
+void __aeabi_unwind_cpp_pr0(void) {
+}

board/tlt536-evm/head.c

@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <types.h>
+
+typedef struct boot_file_head {
+    uint32_t jump_instruction; /* one intruction jumping to real code */
+    uint8_t magic[8];          /* ="eGON.BT0" */
+    uint32_t check_sum;        /* generated by PC */
+    uint32_t *length;          /* generated by LD */
+    uint32_t pub_head_size;    /* the size of boot_file_head_t */
+    uint8_t pub_head_vsn[4];   /* the version of boot_file_head_t */
+    uint32_t *ret_addr;        /* the return value */
+    uint32_t *run_addr;        /* run addr */
+    uint32_t boot_cpu;         /* eGON version */
+    uint8_t platform[8];       /* platform information */
+} boot_file_head_t;
+
+#define BROM_FILE_HEAD_SIZE_OFFSET (((sizeof(boot_file_head_t) + sizeof(int)) / sizeof(int) + 1))
+#define JUMP_INSTRUCTION (BROM_FILE_HEAD_SIZE_OFFSET | 0xEA000000)
+
+#define BOOT0_MAGIC "eGON.BT0"
+#define STAMP_VALUE (0x12345678)
+#define BOOT_PUB_HEAD_VERSION "3000"
+
+extern uint32_t __spl_size[];
+extern uint32_t __code_start_address[];
+
+const __attribute__((section(".boot0_head"))) boot_file_head_t boot_head = {
+        .jump_instruction = JUMP_INSTRUCTION,
+        .magic = BOOT0_MAGIC,
+        .check_sum = STAMP_VALUE,
+        .length = __spl_size,
+        .pub_head_size = sizeof(boot_file_head_t),
+        .pub_head_vsn = BOOT_PUB_HEAD_VERSION,
+        .ret_addr = __code_start_address,
+        .run_addr = __code_start_address,
+        .boot_cpu = 0,
+        .platform = {0, 0, '3', '.', '0', '.', '0', 0},
+};

board/tlt536-evm/hello_world/CMakeLists.txt

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+add_syterkit_app(helloworld 
+    main.c
+)

board/tlt536-evm/hello_world/main.c

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <types.h>
+
+#include <log.h>
+
+#include <common.h>
+
+#include <mmc/sys-sdhci.h>
+
+#include <sys-dram.h>
+#include <sys-sdcard.h>
+#include <sys-i2c.h>
+
+extern sunxi_serial_t uart_dbg;
+
+int main(void) {
+    sunxi_serial_init(&uart_dbg);
+
+    show_banner();
+
+    sunxi_clk_init();
+
+    sunxi_clk_dump();
+
+    printk_info("Hello World!\n");
+
+    abort();
+
+    return 0;
+}