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# Additional address match conditions | ||
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To support disabling registers at runtime and paged/indirect register | ||
files, `vhdmmio` allows you to specify additional conditions for the | ||
address matching logic of each register. This may be useful when not | ||
enough address space is allocated to the register file to fit all the | ||
registers, or when you want to emulate legacy register files such as a | ||
16550 UART. | ||
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This structure supports the following configuration keys. | ||
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## `internal` | ||
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This key specifies the internal signal to use for the match | ||
condition, if applicable. Either this key or `input` must be | ||
specified. | ||
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The following values are supported: | ||
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- `null` (default): no internal is specified, `input` must be specified instead. | ||
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- a string matching `[a-zA-Za-z][a-zA-Z0-9_]*`: a scalar internal with the given name is used for the match condition. | ||
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- a string matching `[a-zA-Za-z][a-zA-Z0-9_]*:[0-9]+`: a vector internal with the given name and width is used for the match condition. | ||
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This key is optional unless required by context. If not specified, the default value (`null`) is used. | ||
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## `input` | ||
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This key specifies the external input signal to use for the match | ||
condition, if applicable. Either this key or `internal` must be | ||
specified. | ||
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The following values are supported: | ||
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- `null` (default): no external input is specified, `internal` must be specified instead. | ||
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- a string matching `[a-zA-Za-z][a-zA-Z0-9_]*`: a scalar input signal with the given name is used for the match condition. | ||
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- a string matching `[a-zA-Za-z][a-zA-Z0-9_]*:[0-9]+`: a vector input signal with the given name and width is used for the match condition. | ||
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This key is optional unless required by context. If not specified, the default value (`null`) is used. | ||
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## `value` | ||
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This key specifies the value that the signal must have for the | ||
logical register to be addressed. | ||
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The following values are supported: | ||
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- `no` (default): the signal value needs to be 0. | ||
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- `yes`: the signal value needs to be 1. | ||
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- an integer: the signal value needs to match the specified value. | ||
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This key is optional unless required by context. If not specified, the default value (`no`) is used. | ||
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## `ignore` | ||
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This key specifies the value that the signal must have for the | ||
logical register to be addressed. | ||
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The following values are supported: | ||
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- `0` (default): all bits must match. | ||
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- a different integer: the bits set in this value are ignored when matching against `value`. | ||
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This key is optional unless required by context. If not specified, the default value (`0`) is used. |
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