Student Number FSM

Problem:

The objective of this design project is to design an FSM that will cycle through my student number via the use of flip-flops and logic gates.

Analytical Implementation:

To begin, I will create a state transition table that shows my BCD Student Number (400312849) in terms of the bits Q1, Q2, Q3, and Q4, as well as a counter C1 that will distinguish between repeated digits, as well as the required states for each flip-flop’s inputs.

While this is the most robust implementation of this design, I must make an effort to simplify the logic so that this FSM will be easier to implement physically. Unfortunately, a few options to simplify this further are not available to me. The options that are not available include having bits whose state are equal to each other (in my case Q1 ≠ Q2 ≠ Q3 ≠ Q4), and I have no bits that are all one value, so I can’t replace any given bit with just a hook up to VCC or GND, and from what I can tell, no bits are uniquely determined by any combination of the other bits.

However, there are still simplifications that I can make. In order to simplify this further, I will change the ‘don’t care’ states of C1 to unique states, and I will try to do that as best as I can (since there are only 8 numbers, one state will not be able to alternate from the last).

From this state transition table, I can determine the necessary inputs (J and !K) for each of my JK flip-flops.

For my K-Maps, I decided to use a mirror layout.

Flip Flop 1:

!K1= 0

SoP implementation of J1:

J1 = (Q3*!Q4) + (Q2*C1)

PoS implementation of J1:

J1 = (Q2 + Q3)(!Q4)(C1)

For flip flop 1, the SoP implementation requires 2 AND gates, and an OR gate. The PoS implementation also requires 2 AND gates, and an OR gate. Therefore, neither implementation is inherently any better or easier than the other, however, if later on I find an input for a different flip flop that uses one of the same operations, I will choose the implementation that matches that. Luckily, !K1 is always a 0 or “don’t care”, so it can just be hooked up directly to GND.

Flip Flop 2:

!K2 = 0

J2 = Q1

For Flip Flop 2, !K2 is always a 0 or “don’t care”, so it can just be hooked up directly to GND, and J2 is always equal to Q1.

Flip Flop 3:

!K3 = 0

SoP implementation of J3:

J3 = !Q1*!Q2*!C1

PoS implementation of J3:

J3 = !Q1*!Q2*!C1

For flip flop 3, the SoP implementation requires 2 AND gates. The PoS implementation also requires 2 AND gates. Therefore, both implementations are the same, so it is trivial which one I choose. Again, !K3 is always a 0 or “don’t care”, so it can just be hooked up directly to GND.

Flip Flop 4:

!K4 = Q3

SoP implementation of J4:

J4 = (!Q1*!Q2*!C1) + (Q2*C1)

PoS implementation of J4:

J4 = (Q2 + !C1)(!Q2 + C1)(!Q1)

For flip flop 4, the J4 SoP implementation requires 3 AND gates and an OR gate. The J4 PoS implementation also requires 2 AND gates and 2 OR gates. I will determine which is more optimal in terms of the rest of the design at the end of this section. In this case, !K4 = Q3.

Flip Flop 5:

!KC1 = 0

SoP implementation of JC1:

JC1 = !Q1 + !Q4

PoS implementation of JC1:

JC1 = !Q1 + !Q4

For flip flop 5, the SoP implementation requires 1 OR gate. The PoS implementation also requires 1 OR gate. Therefore, both implementations are the same, so it is trivial which one I choose. Again, !KC1 is always a 0 or “don’t care”, so it can just be hooked up directly to GND.

Analytical Summary:

Below is a table outlining the most optimal implementation of this FSM based on the SoP and Pos implementations. In total, I will need: 4 AND gates and 3 OR gates.

MultiSim Implementation

Output Timing Diagram:

In the above timing diagram, my student number is numbered in red, while each of the respective bits is labelled. Please note that the double 4 at the beginning is NOT an error, it is the 4-state repeating itself before I un-force the value (e.g. since I have to force the beginning state, it cycles on that value until I un- force it by switching the respective PR/CLR pins from a 0 back to a 1.)

Link to YouTube video of MultiSim running:

https://youtu.be/Bklr8uTOh8Y?t=79

Physical Implementation:

Pre-build Diagram:

PLEASE NOTE: the teal coloured wire on the drawn diagram represents the white wire on my real build (since white doesn’t show up on a white background)

Build Method:

First, I connected the 7SD to the decoder chip, and connected the respective pins using 1kΩ resistors.

Next, I placed all the OR, AND, and JK Flip-Flop chips on the board, and wired up their respective VCC, GND, and PR/CLR pins that won’t be changing, as well as any steady-state inputs to any of the chips.

Next, I wired up all the clock signals as well as the PR/CLR pins that will require forcing.

Then, I wired up all the logic and flipflop connections.

I wired up the clock signal like so, where the yellow wire ran to an OR gate with the other input tied to GND so that I could have a square input wave. The red alligator clip was the output from the HANTEK.

Final Result:

The aforementioned steps left me with a final build that looked like this:

The colour code here was the same as the drawn one.

Fortunately, my circuit worked on the first try, and I was saved from any real debugging. Initially, I had tried to test that the logic was working by manually moving a DC input from high to low for the clock signal, but soon realized that the logic chips expect steady intervals between the clock signal, which a I cannot easily provide by hand.

Presentation Link:

https://youtu.be/Bklr8uTOh8Y