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adrv9026_vcu118: Fix timing #1627

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adrv9026_vcu118: Fix timing #1627

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AndrDragomir
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PR Description

Fix timing issue on adrv9026+vcu118
Waiting for CI builds to confirm the fix

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)
  • Documentation

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

@AndrDragomir
projects/adrv9026/vcu118: Fix timing
b5b85bd 
Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
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@IuliaCMoldovan IuliaCMoldovan Awaiting requested review from IuliaCMoldovan IuliaCMoldovan is a code owner

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@AndrDragomir