XCVR parameters automation

library/xilinx/scripts/xcvr_automation.tcl

@@ -0,0 +1,185 @@
+###############################################################################
+## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+proc adi_xcvr_parameters {file_paths parameters} {
+
+    set default_parameters {
+        "RX_NUM_OF_LANES" "8"
+        "TX_NUM_OF_LANES" "8"
+        "RX_LANE_RATE" "12.5"
+        "TX_LANE_RATE" "12.5"
+        "LINK_MODE" "1"
+        "RX_LANE_INVERT" "0"
+        "TX_LANE_INVERT" "0"
+        "QPLL_REFCLK_DIV" "1"
+        "QPLL_FBDIV_RATIO" "1"
+        "POR_CFG" "16'b0000000000000110"
+        "PPF0_CFG" "16'b0000011000000000"
+        "PPF1_CFG" "16'b0000011000000000"
+        "QPLL_CFG" "27'h0680181"
+        "QPLL_FBDIV" "10'b0000110000"
+        "QPLL_CFG0" "16'b0011001100011100"
+        "QPLL_CFG1" "16'b1101000000111000"
+        "QPLL_CFG1_G3" "16'b1101000000111000"
+        "QPLL_CFG2" "16'b0000111111000000"
+        "QPLL_CFG2_G3" "16'b0000111111000000"
+        "QPLL_CFG3" "16'b0000000100100000"
+        "QPLL_CFG4" "16'b0000000000000011"
+        "QPLL_CP_G3" "10'b0000011111"
+        "QPLL_LPF" "10'b0100110111"
+        "QPLL_CP" "10'b0001111111"
+        "CPLL_FBDIV" "2"
+        "CPLL_FBDIV_4_5" "5"
+        "CPLL_CFG0" "16'b0000000111111010"
+        "CPLL_CFG1" "16'b0000000000100011"
+        "CPLL_CFG2" "16'b0000000000000010"
+        "CPLL_CFG3" "16'b0000000000000000"
+        "CH_HSPMUX" "16'b0010010000100100"
+        "PREIQ_FREQ_BST" "0"
+        "RXPI_CFG0" "16'b0000000000000010"
+        "RXPI_CFG1" "16'b0000000000010101"
+        "RTX_BUF_CML_CTRL" "3'b011"
+        "TX_OUT_DIV" "1"
+        "TX_CLK25_DIV" "20"
+        "TX_PI_BIASSET" "1"
+        "TXPI_CFG" "16'b0000000001010100"
+        "A_TXDIFFCTRL" "5'b10110"
+        "RX_OUT_DIV" "1"
+        "RX_CLK25_DIV" "20"
+        "RX_DFE_LPM_CFG" "16'h0104"
+        "RX_PMA_CFG" "32'h001e7080"
+        "RX_CDR_CFG" "72'h0b000023ff10400020"
+        "RXCDR_CFG0" "16'b0000000000000010"
+        "RXCDR_CFG2" "16'b0000001001101001"
+        "RXCDR_CFG2_GEN2" "10'b1001100101"
+        "RXCDR_CFG2_GEN4" "16'b0000000010110100"
+        "RXCDR_CFG3" "16'b0000000000010010"
+        "RXCDR_CFG3_GEN2" "6'b011010"
+        "RXCDR_CFG3_GEN3" "16'b0000000000010010"
+        "RXCDR_CFG3_GEN4" "16'b0000000000100100"
+        "RXDFE_KH_CFG2" "16'h0200"
+        "RXDFE_KH_CFG3" "16'h4101"
+        "RX_WIDEMODE_CDR" "2'b00"
+        "RX_XMODE_SEL" "1'b1"
+        "TXDRV_FREQBAND" "0"
+        "TXFE_CFG0" "16'b0000001111000010"
+        "TXFE_CFG1" "16'b0110110000000000"
+        "TXFE_CFG2" "16'b0110110000000000"
+        "TXFE_CFG3" "16'b0110110000000000"
+        "TXPI_CFG0" "16'b0000001100000000"
+        "TXPI_CFG1" "16'b0001000000000000"
+        "TXSWBST_EN" "0"
+    }
+
+    set correction_map {
+        "TXOUT_DIV" "TX_OUT_DIV"
+        "RXOUT_DIV" "RX_OUT_DIV"
+        "CPLL_FBDIV_45" "CPLL_FBDIV_4_5"
+        "RXCDR_CFG" "RX_CDR_CFG"
+    }
+
+    set updated_params {}
+    set param_file_path [dict get $file_paths param_file_path]
+    set cfng_file_path [dict get $file_paths cfng_file_path]
+
+    if {$param_file_path ne ""} {
+
+        set param_file_content [read [open $param_file_path r]]
+
+        # Define a regex pattern for extracting the value of QPLL_FBDIV_TOP from $param_file_path
+        set param_pattern {QPLL_FBDIV_TOP =  ([0-9]+);}
+        set match [regexp -inline $param_pattern $param_file_content]
+        set QPLL_FBDIV_TOP [lindex $match 1]
+
+        switch $QPLL_FBDIV_TOP {
+            16 {set QPLL_FBDIV_IN "10'b0000100000"}
+            20 {set QPLL_FBDIV_IN "10'b0000110000"}
+            32 {set QPLL_FBDIV_IN "10'b0001100000"}
+            40 {set QPLL_FBDIV_IN "10'b0010000000"}
+            64 {set QPLL_FBDIV_IN "10'b0011100000"}
+            66 {set QPLL_FBDIV_IN "10'b0101000000"}
+            80 {set QPLL_FBDIV_IN "10'b0100100000"}
+            100 {set QPLL_FBDIV_IN "10'b0101110000"}
+            default {set QPLL_FBDIV_IN "10'b0000000000"}
+        }
+
+        switch $QPLL_FBDIV_TOP {
+            66 {set QPLL_FBDIV_RATIO "1'b0"}
+            default {set QPLL_FBDIV_RATIO "1'b1"}
+        }
+    }
+
+    set file_content [read [open $cfng_file_path r]]
+    set match ""
+    regexp {QPLL[0-9]+} $cfng_file_path match
+
+    # Define a regex pattern for extracting parameters and their values
+    set pattern {'([^']+)' => '([^']+\\?'?[0-9a-hA-H]*)'}
+    set results {}
+    set matches [regexp -all -inline $pattern $file_content]
+
+    for {set i 0} {$i < [llength $matches]} {incr i 3} {
+
+        set param [lindex $matches $i+1]
+        set value [lindex $matches $i+2]
+
+        set cleaned_value [string map {"\\" ""} $value]
+        set corrected_param $param
+
+        if {[dict exists $correction_map $param]} {
+            set corrected_param [dict get $correction_map $param]
+        }
+
+         if {[string first $match $param] == 0} {
+
+            if {[regexp {^(QPLL)[0-9]+(.*)} $param _ prefix rest]} {
+                set corrected_param "${prefix}${rest}"
+            }
+        }
+
+        if {[dict exists $default_parameters $corrected_param]} {
+
+            set default_value [dict get $default_parameters $corrected_param]
+
+            if {$cleaned_value != $default_value} {
+
+                if {[string equal $cleaned_value "QPLL_FBDIV_IN"]} {
+                    set cleaned_value $QPLL_FBDIV_IN
+                }
+                if {[string equal $cleaned_value "QPLL_FBDIV_RATIO"]} {
+                    set cleaned_value $QPLL_FBDIV_RATIO
+                }
+                if {[string equal $corrected_param "PREIQ_FREQ_BST"]} {
+                    set cleaned_value [expr {$cleaned_value}]
+                }
+
+                dict set updated_params $corrected_param $cleaned_value
+            }
+        }
+        lappend results [list $corrected_param $cleaned_value]
+    }
+
+    if {[llength $parameters] > 0} {
+        foreach {key value} $parameters {
+
+            if {[dict exists $default_parameters $key]} {
+                set default_value [dict get $default_parameters $key]
+
+                if {$value != $default_value} {
+                    dict set updated_params $key $value
+                }
+            }
+            if {[dict exists $updated_params $key]} {
+                set default_value [dict get $updated_params $key]
+
+                if {$value != $default_value} {
+                    dict set updated_params $key $value
+                }
+            }    
+        }
+    }
+
+    return $updated_params
+}

projects/adrv9009/common/adrv9009_bd.tcl

@@ -17,6 +17,7 @@ set DATAPATH_WIDTH 4
 source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
 source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl
 source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
+source $ad_hdl_dir/library/xilinx/scripts/xcvr_automation.tcl
 
 # TX parameters
 set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L)      ; # L
@@ -221,18 +222,14 @@ ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
 
 # common cores
 
+global xcvr_config_paths
 
-ad_ip_instance util_adxcvr util_adrv9009_xcvr
-ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_NUM_OF_LANES [expr $MAX_RX_NUM_OF_LANES+$MAX_RX_OS_NUM_OF_LANES]
-ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES
-ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_OUT_DIV 1
-ad_ip_parameter util_adrv9009_xcvr CONFIG.CPLL_FBDIV 4
-ad_ip_parameter util_adrv9009_xcvr CONFIG.CPLL_FBDIV_4_5 5
-ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_CLK25_DIV 10
-ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_CLK25_DIV 10
-ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_PMA_CFG 0x001E7080
-ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020
-ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 0x080
+set util_adxcvr_parameters [adi_xcvr_parameters $xcvr_config_paths [list \
+  RX_NUM_OF_LANES [expr $MAX_RX_NUM_OF_LANES+$MAX_RX_OS_NUM_OF_LANES] \
+  TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES\
+]]
+
+ad_ip_instance util_adxcvr util_adrv9009_xcvr $util_adxcvr_parameters
 
 # xcvr interfaces
 

projects/adrv9009/zc706/system_project.tcl

@@ -13,9 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 #   Use over-writable parameters from the environment.
 #
 #    e.g.
-#      make TX_JESD_L=2 RX_OS_JESD_M=4
-#      make TX_JESD_M=4 TX_JESD_L=2 RX_JESD_M=4 RX_JESD_L=1 RX_OS_JESD_M=2 RX_OS_JESD_L=1
-#      make TX_JESD_M=2 TX_JESD_L=1 RX_JESD_M=4 RX_JESD_L=1 RX_OS_JESD_M=2 RX_OS_JESD_L=1
+#      make PLL_TYPE=CPLL REF_CLK=125 LANE_RATE=5
+
+# Parameter description:
+#   LANE_RATE: Value of lane rate [gbps]
+#   REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40)
+#   PLL_TYPE: The PLL used for driving the link [CPLL/QPLL]
+#
+#   e.g. call for make with parameters
+#   set xcvr_config_paths [adi_xcvr_project [list \
+#     LANE_RATE 5\
+#     REF_CLK 125\
+#     PLL_TYPE CPLL\
+#   ]]
+# The function returns a dictionary with the paths to the `cfng` file
+# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2.
+
+global xcvr_config_paths
+
+set xcvr_config_paths [adi_xcvr_project [list \
+  LANE_RATE [get_env_param LANE_RATE   5] \
+  REF_CLK   [get_env_param REF_CLK   125] \
+  PLL_TYPE  [get_env_param PLL_TYPE CPLL] \
+]]
 
 # Parameter description:
 #   [TX/RX/RX_OS]_JESD_M : Number of converters per link
@@ -46,4 +66,3 @@ adi_project_files adrv9009_zc706 [list \
 
 adi_project_run adrv9009_zc706
 
-

projects/adrv9009/zcu102/system_bd.tcl

@@ -41,5 +41,5 @@ ad_ip_parameter axi_adrv9009_rx_dma CONFIG.FIFO_SIZE 32
 ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.FIFO_SIZE 32
 ad_ip_parameter axi_adrv9009_tx_dma CONFIG.FIFO_SIZE 32
 
-ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 80
-ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_REFCLK_DIV 1
+# ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 80
+# ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_REFCLK_DIV 1

projects/adrv9009/zcu102/system_project.tcl

@@ -13,9 +13,29 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 #   Use over-writable parameters from the environment.
 #
 #    e.g.
-#      make TX_JESD_L=2 RX_OS_JESD_M=4
-#      make TX_JESD_M=4 TX_JESD_L=2 RX_JESD_M=4 RX_JESD_L=1 RX_OS_JESD_M=2 RX_OS_JESD_L=1
-#      make TX_JESD_M=2 TX_JESD_L=1 RX_JESD_M=4 RX_JESD_L=1 RX_OS_JESD_M=2 RX_OS_JESD_L=1
+#      make PLL_TYPE=QPLL0 REF_CLK=250 LANE_RATE=10
+
+# Parameter description:
+#   LANE_RATE: Value of lane rate [gbps]
+#   REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40)
+#   PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1]
+#
+#   e.g. call for make with parameters
+#   set xcvr_config_paths [adi_xcvr_project [list \
+#     LANE_RATE 10\
+#     REF_CLK 250\
+#     PLL_TYPE QPLL0\
+#   ]]
+# The function returns a dictionary with the paths to the `cfng` file
+# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2.
+
+global xcvr_config_paths
+
+set xcvr_config_paths [adi_xcvr_project [list \
+  LANE_RATE [get_env_param LANE_RATE   10] \
+  REF_CLK   [get_env_param REF_CLK    250] \
+  PLL_TYPE  [get_env_param PLL_TYPE QPLL0] \
+]]
 
 # Parameter description:
 #   [TX/RX/RX_OS]_JESD_M : Number of converters per link

projects/adrv9026/common/adrv9026_bd.tcl

@@ -140,24 +140,21 @@ create_bd_port -dir I $rx_ref_clk
 
 # common cores
 
-ad_ip_instance util_adxcvr util_adrv9026_xcvr
-ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
-ad_ip_parameter util_adrv9026_xcvr CONFIG.LINK_MODE $ENCODER_SEL
-ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE
-ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE
-ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_OUT_DIV 1
-ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
-ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_OUT_DIV 1
-ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV 4
-ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV_4_5 5
-ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CLK25_DIV 10
-ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_CLK25_DIV 10
-ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_PMA_CFG 0x001E7080
-ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020
-ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_FBDIV 40
-ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_REFCLK_DIV 1
-ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 6
-ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_INVERT 15
+source $ad_hdl_dir/library/xilinx/scripts/xcvr_automation.tcl
+
+global xcvr_config_paths
+
+set util_adxcvr_parameters [adi_xcvr_parameters $xcvr_config_paths [list \
+  LINK_MODE $ENCODER_SEL \
+  RX_LANE_RATE $RX_LANE_RATE \
+  TX_LANE_RATE $TX_LANE_RATE \
+  TX_LANE_INVERT 6 \
+  RX_LANE_INVERT 15 \
+  RX_NUM_OF_LANES $RX_NUM_OF_LANES \
+  TX_NUM_OF_LANES $TX_NUM_OF_LANES\
+]]
+
+ad_ip_instance util_adxcvr util_adrv9026_xcvr $util_adxcvr_parameters
 
 ad_connect  $sys_cpu_resetn util_adrv9026_xcvr/up_rstn
 ad_connect  $sys_cpu_clk util_adrv9026_xcvr/up_clk

projects/adrv9026/vcu118/system_project.tcl

@@ -12,6 +12,31 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 #
 #   Use over-writable parameters from the environment.
 #
+#    e.g.
+#      make PLL_TYPE=QPLL0 REF_CLK=245.75 LANE_RATE=9.83
+
+# Parameter description:
+#   LANE_RATE: Value of lane rate [gbps]
+#   REF_CLK: Value of the reference clock [MHz] (usually LANE_RATE/20 or LANE_RATE/40)
+#   PLL_TYPE: The PLL used for driving the link [CPLL/QPLL0/QPLL1]
+#
+#   e.g. call for make with parameters
+#   set xcvr_config_paths [adi_xcvr_project [list \
+#     LANE_RATE 9.83\
+#     REF_CLK 245.75\
+#     PLL_TYPE QPLL0\
+#   ]]
+# The function returns a dictionary with the paths to the `cfng` file
+# containing the modified parameters and to the `_common.v` file for extracting the value of the `QPLL_FBDIV_TOP` parameter for GTXE2.
+
+global xcvr_config_paths
+
+set xcvr_config_paths [adi_xcvr_project [list \
+  LANE_RATE [get_env_param LANE_RATE  9.83] \
+  REF_CLK   [get_env_param REF_CLK  245.75] \
+  PLL_TYPE  [get_env_param PLL_TYPE  QPLL0] \
+]]
+
 # Parameter description:
 #   [TX/RX/RX_OS]_JESD_M : Number of converters per link
 #   [TX/RX/RX_OS]_JESD_L : Number of lanes per link
@@ -41,3 +66,4 @@ adi_project_files adrv9026_vcu118 [list \
 ## To improve timing of the BRAM buffers
 
 adi_project_run adrv9026_vcu118
+