links to schematics

docs/_docs/build-06-loader.md

@@ -97,8 +97,13 @@ HR and HL signals.  Any other signals from ROM 2 that are not controlled by the
 must have pull-up or pull-down resistors if they need to be in known states while the
 Loader is active.
 
+The Loader Active signal is also used to hold the Ring Counter in reset so that it does
+not cycle while the loader is driving the clock.
+
 ## Loader implementation
 
+[![Loader Schematic](../../assets/images/loader-schematic.png "loader/debugger schematic logic"){:width="720px"}](../../assets/images/loader-schematic.png)
+
 The loader uses an Arduino Nano clone.  The Nano form factor was chosen over the more
 common Uno because the small form factor can be installed directly on the breadboards with
 the rest of the NQSAP.  Rather than installing male pins on the Nano, female socket strips

docs/_docs/build-07-ring-counter.md

@@ -41,6 +41,10 @@ reset inputs - the RST line is tied to the system RST to do an immediate clear w
 entire computer is reset and the LOAD line is tied to a control line from the uCode ROM to
 do a synchronous clear at the end of an instruction cycle.
 
+The wiring for the Ring Counter is included in the
+[Microcode ROMs schematic](../../assets/images/microcode-roms-schematic.png "microcode ROMs schematic")
+on the [Microcode ROMs and Control Logic](../control) documentation page.
+
 The NQSAP Ring Counter uses only two chips.  The 74LS161 is the 4-bit counter that keeps
 track of the current microinstruction step (T cycle).  The lower three bits of this
 counter drive the A0..A2 address lines of each microcode EEPROM.  

docs/_docs/build-09-control.md

@@ -24,16 +24,18 @@ The fifteen ROM address bits are allocated as follows:
 
 ```
 A14 A13   A12 A11   A10 A9  A8  A7  A6  A5  A4  A3    A2  A1  A0
- R   R     F   F     I   I   I   I   I   I   I   I     T   T   T
+ R   R     X   X     I   I   I   I   I   I   I   I     T   T   T
 ```
 
  |Bits  |Count| Use                | Source             |
  |:---: |:---:|:---                |:--                 |
  |14..13|2    |ROM select          |Hardwired           |
- |12..11|2    |Flags               |Flags register      |
+ |12..11|2    |Not used            |Not in use          |
  |10..3 |8    |Instruction (opcode)|Instruction Register|
  |2..0  |3    |T Cycle             |Ring Counter        |
 
+A future build may expand the T Cycle bits to four, expanding the number of
+microinstruction steps from eight to sixteen.
 
 ## Bus control multiplexing
 
@@ -50,6 +52,13 @@ selected at a time
 also use active low controls, reducing the number of inverters needed on microcode ROM
 control signals
 
+## Schematic
+
+[![Microcode ROMs and Control Logic schematic](../../assets/images/microcode-roms-schematic.png "microcode ROMs schematic"){:width="720px"}](../../assets/images/microcode-roms-schematic.png)
+
+The schematic for the microcode ROMs shows the 28C256 ROMs and the register decode logic.
+The Ring Counter (step counter) and Instruction Register are also included.
+
 ## Bill of Materials
 
 * 28C256 32Kx8 EEPROM (4)