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StreamMemoryReader: fix formal, add memory as submodule
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rroohhh authored and anuejn committed Jan 7, 2024
1 parent e861616 commit 52126ba
Showing 1 changed file with 2 additions and 2 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ def test_hello_world(self):
m = Module()

address_stream = PacketizedStream(8)
mem = Memory(width=32, depth=128, init=[i + 2 for i in range(128)])
mem = m.submodules.memory = Memory(width=32, depth=128, init=[i + 2 for i in range(128)])
reader = m.submodules.reader = StreamMemoryReader(address_stream, mem)

def write_process():
Expand All @@ -36,4 +36,4 @@ def test_output_stream_contract(self):
input_stream = PacketizedStream(8)
mem = Memory(width=32, depth=128, init=[i + 2 for i in range(128)])
dut = StreamMemoryReader(input_stream, mem)
verify_stream_output_contract(dut, support_modules=(LegalStreamSource(input_stream),))
verify_stream_output_contract(dut, support_modules=(LegalStreamSource(input_stream), mem))

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