Skip to content

Issues: apl-cornell/PDL

New issue

Have a question about this project? # for a free GitHub account to open an issue and contact its maintainers and the community.

#

By clicking “#”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? # to your account

21 Open 19 Closed
21 Open 19 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Question about tests
#76 opened Mar 16, 2023 by wang-hanmo
SpecTable force clear method to conflict with allocation method
#73 opened Dec 15, 2022 by dz333
@dz333
Utilities.scala a bit large
#70 opened Jan 26, 2022 by charles-rs
Enable Full Out-Of-Order Execution enhancement New feature or request
#69 opened Jan 4, 2022 by dz333
Generate SizedFIFOFs for pipeline coordination edges enhancement New feature or request good first issue Good for newcomers
#67 opened Dec 15, 2021 by dz333
Create a CAM primitive (and actually add Structs/Record Types) enhancement New feature or request
#65 opened Dec 13, 2021 by dz333
Replace internal representation of constants - Java Integers can only represent 32 bit ints bug Something isn't working good first issue Good for newcomers
#59 opened Nov 16, 2021 by dz333
Reduce Extra Cycle Latency of Pipeline Calls code generation Related to Generating RTL Code enhancement New feature or request
#49 opened Sep 28, 2021 by dz333
1
Improve location permanence in the AST enhancement New feature or request good first issue Good for newcomers
#48 opened Sep 26, 2021 by charles-rs
2
Refactor Combinational Reads to Be Their Own Command enhancement New feature or request good first issue Good for newcomers
#47 opened Sep 20, 2021 by dz333
Optimize Control Logic Generation for In-order Pipeline Regions enhancement New feature or request
#40 opened Aug 10, 2021 by dz333
Faster Testing for BSV Simulation enhancement New feature or request
#34 opened Jul 15, 2021 by dz333
Refactor BSV EHR library to use CRegs rtl library Verilog/BSV code for use as a library that compiler targets
#32 opened Jul 14, 2021 by dz333
1
Speculation Kill Logic Can Cause Deadlock bug Something isn't working enhancement New feature or request
#24 opened Jun 18, 2021 by dz333
@dz333
1
Make Memory Addressing Independent of Read Size enhancement New feature or request
#23 opened Jun 8, 2021 by dz333
Allow for Richer Conditional Speculation enhancement New feature or request
#22 opened Jun 4, 2021 by dz333
Speculative Lock Region Bug (Low Priority) bug Something isn't working
#21 opened Jun 4, 2021 by dz333
Variable Names that Conflict With BSV Keywords Cause Errors bug Something isn't working code generation Related to Generating RTL Code good first issue Good for newcomers
#10 opened Apr 27, 2021 by dz333
Refactor Bluespec Parameters into Config Infrastructure code generation Related to Generating RTL Code enhancement New feature or request
#9 opened Apr 27, 2021 by dz333
Create website for PDL documentation Improvements or additions to documentation
#4 opened Mar 5, 2021 by dz333
@kevzhumba
Create Parseable IR for StageGraphs enhancement New feature or request
#3 opened Mar 5, 2021 by dz333
ProTip! Add no:assignee to see everything that’s not assigned.