Conditionally IMemRecv pushed back too far after Stage merging

[dz333]

The following generates the wrong code at the moment:

split {
    case(a): {
       wdata <- mem[addr];
    ...
    default: {
     wdata <- 3;
     }
---
    x = (a) ? wdata : wdata + 1;

The computation for x uses the default wdata value instead of the one from the memory read, becuase the IMemRecv() command is ordered after the computation of x in the stage command list. This should not be generated in this order.

This is likely a result of stage merging as well -> when the IMemRecv is merged into the stage assigning to x, it should be at the beginning of the command list.

[dz333]

Attached is an example PDL circuit that will cause this exact issue:
lateRecv.txt

In the following snippet from the output of the PDL compiler (generated BSV code):

    Int#(32) _Stage__4_wdata = fifo_Start_TO_Stage__4.first.wdata;
    ...
    Int#(32) _Stage__4_x = ?;
    _Stage__4_x = ( ( _Stage__4_cond == 2'd0 ) ? _Stage__4_wdata : ( _Stage__4_wdata + 32'd1 ) );
    if ( ( _Stage__4___condStage__3 == 1'd0 ))
    begin
        _Stage__4_wdata = mem.peekResp(_Stage__4__request_0);
    end

x ignores the result coming back from memory (i.e., mem.peekResp(...)).

The compiler should generate all code that writes to a variable, before it is used in that stage.
The fixed version would simply have the conditional assignment to wdata be moved earlier:

    Int#(32) _Stage__4_wdata = fifo_Start_TO_Stage__4.first.wdata;
    if ( ( _Stage__4___condStage__3 == 1'd0 ))
    begin
        _Stage__4_wdata = mem.peekResp(_Stage__4__request_0);
    end
    ...
    Int#(32) _Stage__4_x = ?;
    _Stage__4_x = ( ( _Stage__4_cond == 2'd0 ) ? _Stage__4_wdata : ( _Stage__4_wdata + 32'd1 ) );
  

[dz333]

Resolved by #50