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Use try_from instead of the cast crate. #172

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Merged
merged 3 commits into from
Jun 9, 2019
Merged

Use try_from instead of the cast crate. #172

merged 3 commits into from
Jun 9, 2019

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arilotter
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try_from is stable now, so cast is unnecessary.
This closes #169

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Looks good! It looks like there are 2 more crates which could use converting from cast to try_from: wasmtime-wasi-c and wasmtime-runtime. Do you think you'd be able to make those changes in this PR? :-)

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@kubkon I've converted those two crates too!
I notice there were places in the code that had the pattern

#[cfg(target_pointer_width = "32")]
let sig_id = VMSharedSignatureIndex::new(cast::u32(len));
#[cfg(target_pointer_width = "64")]
let sig_id = VMSharedSignatureIndex::new(cast::u32(len).unwrap());

I assume that this is written as such because the cast crate does conditional compilation too, and provides a different signature based on the target pointer size - Is there any problem with doing an unconditional unwrap, since the try_from trait always provides a Result?

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kubkon commented Jun 9, 2019

@kubkon I've converted those two crates too!
I notice there were places in the code that had the pattern

#[cfg(target_pointer_width = "32")]
let sig_id = VMSharedSignatureIndex::new(cast::u32(len));
#[cfg(target_pointer_width = "64")]
let sig_id = VMSharedSignatureIndex::new(cast::u32(len).unwrap());

I assume that this is written as such because the cast crate does conditional compilation too, and provides a different signature based on the target pointer size

Correct!

Is there any problem with doing an unconditional unwrap, since the try_from trait always provides a Result?

None at all. To the best of my knowledge, we can safely chuck away the cfgs here and just have a single version using try_from.

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Alright, then this should be ready to merge 😁 I made sure to cargo fmt too

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kubkon commented Jun 9, 2019

Looks great, thanks! For the future, you can run format-all.sh to do the formatting for you, and test-all.sh to check the formatting, builds, and run some basic spec tests ;-)

@kubkon kubkon merged commit 8dc1d90 into bytecodealliance:master Jun 9, 2019
pchickey added a commit to pchickey/wasmtime that referenced this pull request May 12, 2023
* delete adapter src/main.o: this was accidentally left out of bytecodealliance#165

* move adapter, byte-array, and verify to a new workspace

* rename byte-array crate to a name available on crates.io

* add a readme for verify, also give it a slightly better name

* CI: wit dep check in its own step, verify before publish, trim down publication

* reactor-tests: delete deps symlinks

* reactor-tests: manage wit with wit-deps

* test: dont set default toolchain to nightly

* wit-deps lock adapter

* wit-deps lock reactor-tests

wit-deps doesnt manage these for some reason
pchickey added a commit to pchickey/wasmtime that referenced this pull request May 16, 2023
* delete adapter src/main.o: this was accidentally left out of bytecodealliance#165

* move adapter, byte-array, and verify to a new workspace

* rename byte-array crate to a name available on crates.io

* add a readme for verify, also give it a slightly better name

* CI: wit dep check in its own step, verify before publish, trim down publication

* reactor-tests: delete deps symlinks

* reactor-tests: manage wit with wit-deps

* test: dont set default toolchain to nightly

* wit-deps lock adapter

* wit-deps lock reactor-tests

wit-deps doesnt manage these for some reason
avanhatt pushed a commit to wellesley-prog-sys/wasmtime that referenced this pull request Oct 23, 2024
Model the `Reg` type on AArch64 as unknown bitvector width.

Reverses bytecodealliance#108. The motivation for this is the need to model vector
intructions, where `Reg` is also used to represent ARM `Z` 128-bit
registers. The type inference problems that necessitated the 64-bit type
before have now been fixed by a combination of bytecodealliance#167 and bytecodealliance#171.

Updates avanhatt#46 avanhatt#34
avanhatt pushed a commit to wellesley-prog-sys/wasmtime that referenced this pull request Oct 23, 2024
Model the `Reg` type on AArch64 as unknown bitvector width.

Reverses bytecodealliance#108. The motivation for this is the need to model vector
intructions, where `Reg` is also used to represent ARM `Z` 128-bit
registers. The type inference problems that necessitated the 64-bit type
before have now been fixed by a combination of bytecodealliance#167 and bytecodealliance#171.

Updates avanhatt#46 avanhatt#34
dicej added a commit to dicej/wasmtime that referenced this pull request Jun 3, 2025
Fixes bytecodealliance#172

Co-authored-by: Luke Wagner <mail@lukewagner.name>
Signed-off-by: Joel Dice <joel.dice@fermyon.com>
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Use try_from
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