Revert "Single Port Memories (#1610)"

This reverts commit fab34ab.

Dockerfile

@@ -53,8 +53,8 @@ RUN python3 setup.py bdist_wheel && python3 -m pip install dist/tvm-*.whl
 WORKDIR /home
 RUN git  clone https://github.com/cucapra/dahlia.git
 WORKDIR /home/dahlia
-## Checkout specific version. Fetch before checkout because clone might be cached.
-RUN git fetch --all && git checkout 88e05e5
+## Checkout specific version
+RUN git checkout 51954e7
 RUN sbt "; getHeaders; assembly"
 
 # Add the Calyx source code from the build context

calyx-ir/src/common.rs

@@ -32,9 +32,9 @@ impl<T: GetName> WRC<T> {
     pub fn upgrade(&self) -> RRC<T> {
         let Some(r) = self.internal.upgrade() else {
             #[cfg(debug_assertions)]
-            unreachable!("weak reference points to a dropped value. Original object's name: `{}'", self.debug_name);
+            unreachable!("weak reference points to a dropped. Original object's name: `{}'", self.debug_name);
             #[cfg(not(debug_assertions))]
-            unreachable!("weak reference points to a dropped value.");
+            unreachable!("weak reference points to a dropped.");
         };
         r
     }

calyx-ir/src/component.rs

@@ -231,14 +231,6 @@ impl Component {
         self.namegen.gen_name(prefix)
     }
 
-    /// Check whether this component is purely structural, i.e. has no groups or control
-    pub fn is_structural(&self) -> bool {
-        self.groups.is_empty()
-            && self.comb_groups.is_empty()
-            && self.static_groups.is_empty()
-            && self.control.borrow().is_empty()
-    }
-
     /// Check whether this is a static component.
     /// A static component is a component which has a latency field.
     pub fn is_static(&self) -> bool {
@@ -324,7 +316,7 @@ impl Component {
 #[derive(Debug)]
 pub struct IdList<T: GetName>(LinkedHashMap<Id, RRC<T>>);
 
-/// Simple iter impl delegating to the [`Values`](linked_hash_map::Values).
+/// Simple into-iter impl delegating to the [`Values`](linked_hash_map::Values).
 impl<'a, T: GetName> IntoIterator for &'a IdList<T> {
     type Item = &'a RRC<T>;
 

calyx-opt/src/default_passes.rs

@@ -3,9 +3,9 @@ use crate::passes::{
     AddGuard, Canonicalize, CellShare, ClkInsertion, CollapseControl, CombProp,
     CompileInvoke, CompileRepeat, CompileStatic, CompileStaticInterface,
     CompileSync, CompileSyncWithoutSyncReg, ComponentInliner, DataPathInfer,
-    DeadAssignmentRemoval, DeadCellRemoval, DeadGroupRemoval, DefaultAssigns,
-    DiscoverExternal, Externalize, GoInsertion, GroupToInvoke, GroupToSeq,
-    HoleInliner, InferShare, LowerGuards, MergeAssign, Papercut, ParToSeq,
+    DeadAssignmentRemoval, DeadCellRemoval, DeadGroupRemoval, DiscoverExternal,
+    Externalize, GoInsertion, GroupToInvoke, GroupToSeq, HoleInliner,
+    InferShare, LowerGuards, MergeAssign, Papercut, ParToSeq,
     RegisterUnsharing, RemoveIds, ResetInsertion, SimplifyStaticGuards,
     SimplifyWithControl, StaticInference, StaticInliner, StaticPromotion,
     SynthesisPapercut, TopDownCompileControl, UnrollBounded, WellFormed,
@@ -59,7 +59,6 @@ impl PassManager {
         pm.register_pass::<ResetInsertion>()?;
         pm.register_pass::<MergeAssign>()?;
         pm.register_pass::<WrapMain>()?;
-        pm.register_pass::<DefaultAssigns>()?;
 
         // Enabled in the synthesis compilation flow
         pm.register_pass::<SynthesisPapercut>()?;
@@ -135,7 +134,6 @@ impl PassManager {
                 ClkInsertion,
                 ResetInsertion,
                 MergeAssign,
-                DefaultAssigns,
             ]
         );
 

calyx-opt/src/passes/mod.rs

@@ -35,7 +35,6 @@ mod sync;
 mod add_guard;
 mod compile_static_interface;
 mod data_path_infer;
-mod default_assigns;
 mod discover_external;
 mod simplify_with_control;
 mod synthesis_papercut;
@@ -82,7 +81,6 @@ pub use sync::CompileSyncWithoutSyncReg;
 // pub use simplify_guards::SimplifyGuards;
 pub use add_guard::AddGuard;
 pub use compile_static_interface::CompileStaticInterface;
-pub use default_assigns::DefaultAssigns;
 pub use synthesis_papercut::SynthesisPapercut;
 pub use top_down_compile_control::TopDownCompileControl;
 pub use unroll_bound::UnrollBounded;

calyx-opt/src/passes/papercut.rs

@@ -28,30 +28,6 @@ pub struct Papercut {
     cont_cells: HashSet<ir::Id>,
 }
 
-impl Papercut {
-    #[allow(unused)]
-    /// String representation of the write together and read together specifications.
-    /// Used for debugging. Should not be relied upon by external users.
-    fn fmt_write_together_spec(&self) -> String {
-        self.write_together
-            .iter()
-            .map(|(prim, writes)| {
-                let writes = writes
-                    .iter()
-                    .map(|write| {
-                        write
-                            .iter()
-                            .sorted()
-                            .map(|port| format!("{port}"))
-                            .join(", ")
-                    })
-                    .join("; ");
-                format!("{}: [{}]", prim, writes)
-            })
-            .join("\n")
-    }
-}
-
 impl ConstructVisitor for Papercut {
     fn from(ctx: &ir::Context) -> CalyxResult<Self> {
         let write_together =
@@ -256,7 +232,7 @@ impl Papercut {
                             .join(", ");
                         let msg =
                             format!("Required signal not driven inside the group.\
-                                        \nWhen reading the port `{}.{}', the ports [{}] must be written to.\
+                                        \nWhen read the port `{}.{}', the ports [{}] must be written to.\
                                         \nThe primitive type `{}' requires this invariant.",
                                     inst,
                                     read,
@@ -269,35 +245,30 @@ impl Papercut {
         }
         for ((inst, comp_type), writes) in all_writes {
             if let Some(spec) = self.write_together.get(&comp_type) {
-                // For each write together spec.
                 for required in spec {
                     // It should either be the case that:
                     // 1. `writes` contains no writes that overlap with `required`
                     //     In which case `required - writes` == `required`.
                     // 2. `writes` contains writes that overlap with `required`
                     //     In which case `required - writes == {}`
-                    let mut diff: HashSet<_> =
-                        required.difference(&writes).copied().collect();
-                    if diff.is_empty() || diff == *required {
-                        continue;
+                    let mut diff = required - &writes;
+                    if !diff.is_empty() && diff != *required {
+                        let first = writes.iter().sorted().next().unwrap();
+                        let missing = diff
+                            .drain()
+                            .sorted()
+                            .map(|port| format!("{}.{}", inst, port))
+                            .join(", ");
+                        let msg =
+                            format!("Required signal not driven inside the group.\
+                                        \nWhen writing to the port `{}.{}', the ports [{}] must also be written to.\
+                                        \nThe primitive type `{}' requires this invariant.",
+                                    inst,
+                                    first,
+                                    missing,
+                                    comp_type);
+                        return Err(Error::papercut(msg));
                     }
-
-                    let first =
-                        writes.intersection(required).sorted().next().unwrap();
-                    let missing = diff
-                        .drain()
-                        .sorted()
-                        .map(|port| format!("{}.{}", inst, port))
-                        .join(", ");
-                    let msg =
-                        format!("Required signal not driven inside the group. \
-                                 When writing to the port `{}.{}', the ports [{}] must also be written to. \
-                                 The primitive type `{}' specifies this using a @write_together spec.",
-                                inst,
-                                first,
-                                missing,
-                                comp_type);
-                    return Err(Error::papercut(msg));
                 }
             }
         }

calyx-py/calyx/builder.py

@@ -605,8 +605,8 @@ def mem_read_seq_d1(self, mem, i, groupname=None):
         groupname = groupname or f"read_from_{mem.name()}"
         with self.group(groupname) as read_grp:
             mem.addr0 = i
-            mem.content_en = 1
-            read_grp.done = mem.done
+            mem.read_en = 1
+            read_grp.done = mem.read_done
         return read_grp
 
     def mem_write_seq_d1_to_reg(self, mem, reg, groupname=None):
@@ -631,8 +631,7 @@ def mem_store_seq_d1(self, mem, i, val, groupname=None):
             mem.addr0 = i
             mem.write_en = 1
             mem.write_data = val
-            mem.content_en = 1
-            store_grp.done = mem.done
+            store_grp.done = mem.write_done
         return store_grp
 
     def mem_load_to_mem(self, mem, i, ans, j, groupname=None):
@@ -1100,7 +1099,7 @@ def infer_width(self, port_name) -> int:
                 return inst.args[2]
             if port_name == "in":
                 return inst.args[0]
-            if prim == "seq_mem_d1" and port_name == "content_en":
+            if prim == "seq_mem_d1" and port_name == "read_en":
                 return 1
         if prim in (
             "std_mult_pipe",

examples/futil/dot-product.expect

@@ -115,8 +115,6 @@ component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
     A_read0_0.reset = reset;
     A_read0_0.in = fsm.out == 4'd0 & early_reset_static_seq_go.out ? A0.read_data;
     A_read0_0.in = fsm.out == 4'd4 & early_reset_static_seq_go.out ? mult_pipe0.out;
-    A0.write_en = 1'd0;
-    B0.write_en = 1'd0;
   }
   control {}
 }

examples/futil/vectorized-add.expect

@@ -105,8 +105,6 @@ component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
     A_read0_0.clk = clk;
     A_read0_0.reset = reset;
     A_read0_0.in = fsm.out == 3'd0 & early_reset_static_seq_go.out ? A0.read_data;
-    A0.write_en = 1'd0;
-    B0.write_en = 1'd0;
   }
   control {}
 }