Some tests for simplify-invoke-with. found bugs

calyxir · Mar 7, 2025 · 7199858 · 7199858
1 parent eef79a7
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Showing 8 changed files with 248 additions and 2 deletions.
diff --git a/tests/passes/simplify-invoke-with/basic.expect b/tests/passes/simplify-invoke-with/basic.expect
@@ -11,7 +11,6 @@ component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
     x2 = std_reg(32);
     y2 = std_reg(32);
     mul2 = std_mult_pipe(32);
-    mul3 = std_mult_pipe(32);
     @control @generated @protected mul_active = std_wire(1);
     @control @generated @protected mul2_active = std_wire(1);
   }

diff --git a/tests/passes/simplify-invoke-with/basic.futil b/tests/passes/simplify-invoke-with/basic.futil
@@ -13,7 +13,6 @@ component main() -> () {
     x2 = std_reg(32);
     y2 = std_reg(32);
     mul2 = std_mult_pipe(32);
-    mul3 = std_mult_pipe(32);
 
     @control @generated @protected mul_active = std_wire(1);
     @control @generated @protected mul2_active = std_wire(1);

diff --git a/tests/passes/simplify-invoke-with/conflicting-invokes.expect b/tests/passes/simplify-invoke-with/conflicting-invokes.expect
@@ -0,0 +1,33 @@
+import "primitives/core.futil";
+import "primitives/memories/seq.futil";
+import "primitives/binary_operators.futil";
+component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
+  cells {
+    r = std_reg(32);
+    x = std_reg(32);
+    y = std_reg(32);
+    mul = std_mult_pipe(32);
+    r2 = std_reg(32);
+    x2 = std_reg(32);
+    y2 = std_reg(32);
+    mul2 = std_mult_pipe(32);
+    @control @generated @protected mul_active = std_wire(1);
+  }
+  wires {
+    comb group comb_invoke {
+      mul_active.in = !mul.done ? 1'd1;
+    }
+  }
+  control {
+    seq {
+      invoke mul(
+        left = x.out,
+        right = y.out
+      )() with comb_invoke;
+      invoke mul2(
+        left = x2.out,
+        right = y2.out
+      )() with comb_invoke;
+    }
+  }
+}
diff --git a/tests/passes/simplify-invoke-with/conflicting-invokes.futil b/tests/passes/simplify-invoke-with/conflicting-invokes.futil
@@ -0,0 +1,30 @@
+// -p simplify-invoke-with
+
+import "primitives/core.futil";
+import "primitives/memories/seq.futil";
+import "primitives/binary_operators.futil";
+component main() -> () {
+  cells {
+    r = std_reg(32);
+    x = std_reg(32);
+    y = std_reg(32);
+    mul = std_mult_pipe(32);
+    r2 = std_reg(32);
+    x2 = std_reg(32);
+    y2 = std_reg(32);
+    mul2 = std_mult_pipe(32);
+
+    @control @generated @protected mul_active = std_wire(1);
+  }
+  wires {
+    comb group comb_invoke {
+      mul_active.in = !mul.done ? 1'd1;
+    }
+   }
+  control {
+    seq {
+      invoke mul(left = x.out, right = y.out)() with comb_invoke;
+      invoke mul2(left = x2.out, right = y2.out)() with comb_invoke;
+     }
+  }
+}
diff --git a/tests/passes/simplify-invoke-with/conflicting-with-while.expect b/tests/passes/simplify-invoke-with/conflicting-with-while.expect
@@ -0,0 +1,55 @@
+import "primitives/core.futil";
+import "primitives/memories/seq.futil";
+import "primitives/binary_operators.futil";
+component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
+  cells {
+    r = std_reg(32);
+    x = std_reg(32);
+    y = std_reg(32);
+    mul = std_mult_pipe(32);
+    r2 = std_reg(32);
+    x2 = std_reg(32);
+    y2 = std_reg(32);
+    mul2 = std_mult_pipe(32);
+    lt = std_lt(32);
+    lt_reg = std_reg(1);
+    @control @generated @protected mul_active = std_wire(1);
+  }
+  wires {
+    group init_x {
+      x.in = 32'd3;
+      x.write_en = 1'd1;
+      init_x[done] = x.done;
+    }
+    group init_y {
+      y.in = 32'd5;
+      y.write_en = 1'd1;
+      init_y[done] = y.done;
+    }
+    group write_r {
+      r.in = mul.out;
+      r.write_en = 1'd1;
+      write_r[done] = r.done;
+    }
+    comb group comb_group {
+      lt.left = r.out;
+      lt.right = 32'd25;
+      mul_active.in = !mul.done ? 1'd1;
+    }
+  }
+  control {
+    seq {
+      init_x;
+      init_y;
+      while lt.out with comb_group {
+        seq {
+          invoke mul(
+            left = x.out,
+            right = y.out
+          )() with comb_group;
+          write_r;
+        }
+      }
+    }
+  }
+}
diff --git a/tests/passes/simplify-invoke-with/conflicting-with-while.futil b/tests/passes/simplify-invoke-with/conflicting-with-while.futil
@@ -0,0 +1,54 @@
+// -p simplify-invoke-with
+
+import "primitives/core.futil";
+import "primitives/memories/seq.futil";
+import "primitives/binary_operators.futil";
+component main() -> () {
+  cells {
+    r = std_reg(32);
+    x = std_reg(32);
+    y = std_reg(32);
+    mul = std_mult_pipe(32);
+    r2 = std_reg(32);
+    x2 = std_reg(32);
+    y2 = std_reg(32);
+    mul2 = std_mult_pipe(32);
+    lt = std_lt(32);
+    lt_reg = std_reg(1);
+
+
+    @control @generated @protected mul_active = std_wire(1);
+  }
+  wires {
+    comb group comb_group {
+      lt.left = r.out;
+      lt.right = 32'd25;
+      mul_active.in = !mul.done ? 1'd1;
+    }
+    group init_x {
+      x.in = 32'd3;
+      x.write_en = 1'd1;
+      init_x[done] = x.done;      
+    }
+    group init_y {
+      y.in = 32'd5;
+      y.write_en = 1'd1;
+      init_y[done] = y.done;
+    }
+    group write_r {
+      r.in = mul.out;
+      r.write_en = 1'd1;
+      write_r[done] = r.done;
+    }
+   }
+  control {
+    seq {
+      init_x;
+      init_y;
+      while lt.out with comb_group {
+        invoke mul(left = x.out, right = y.out)() with comb_group;
+	write_r;
+      }
+     }
+  }
+}
diff --git a/tests/passes/simplify-invoke-with/two_dup_invokes.expect b/tests/passes/simplify-invoke-with/two_dup_invokes.expect
@@ -0,0 +1,41 @@
+import "primitives/core.futil";
+import "primitives/memories/seq.futil";
+import "primitives/binary_operators.futil";
+component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
+  cells {
+    r = std_reg(32);
+    x = std_reg(32);
+    y = std_reg(32);
+    mul = std_mult_pipe(32);
+    r2 = std_reg(32);
+    x2 = std_reg(32);
+    y2 = std_reg(32);
+    mul2 = std_mult_pipe(32);
+    @control @generated @protected mul_active = std_wire(1);
+    @control @generated @protected mul2_active = std_wire(1);
+  }
+  wires {
+    comb group comb_invoke {
+      mul_active.in = !mul.done ? 1'd1;
+    }
+    comb group comb_invoke1 {
+      mul2_active.in = !1'd0 ? 1'd1;
+    }
+  }
+  control {
+    seq {
+      invoke mul(
+        left = x.out,
+        right = y.out
+      )() with comb_invoke;
+      invoke mul2(
+        left = x2.out,
+        right = y2.out
+      )() with comb_invoke1;
+      invoke mul(
+        left = x.out,
+        right = y.out
+      )() with comb_invoke;
+    }
+  }
+}
diff --git a/tests/passes/simplify-invoke-with/two_dup_invokes.futil b/tests/passes/simplify-invoke-with/two_dup_invokes.futil
@@ -0,0 +1,35 @@
+// -p simplify-invoke-with
+
+import "primitives/core.futil";
+import "primitives/memories/seq.futil";
+import "primitives/binary_operators.futil";
+component main() -> () {
+  cells {
+    r = std_reg(32);
+    x = std_reg(32);
+    y = std_reg(32);
+    mul = std_mult_pipe(32);
+    r2 = std_reg(32);
+    x2 = std_reg(32);
+    y2 = std_reg(32);
+    mul2 = std_mult_pipe(32);
+
+    @control @generated @protected mul_active = std_wire(1);
+    @control @generated @protected mul2_active = std_wire(1);
+  }
+  wires {
+    comb group comb_invoke {
+      mul_active.in = !mul.done ? 1'd1;
+    }
+    comb group comb_invoke1 {
+      mul2_active.in = !mul2.done ? 1'd1;
+    }
+   }
+  control {
+    seq {
+      invoke mul(left = x.out, right = y.out)() with comb_invoke;
+      invoke mul2(left = x2.out, right = y2.out)() with comb_invoke1;
+      invoke mul(left = x.out, right = y.out)() with comb_invoke;      
+     }
+  }
+}