Add Verilog reserved word: wait

[polybeandip]

Here's an example program, where we name a cell wait:

# making a cell named "wait"
import "primitives/core.futil";

component main() -> () {
  cells {
    wait = std_reg(32);
    add = std_add(32);
  }
  wires {
   static<1> group write {
     add.left = wait.out;
     add.right = 32'd1;
     wait.write_en = 1'b1;
     wait.in = add.out;
   }
  }
  control {
      write;
  }
}

Running this with fud exec <file_name>.futil --to dat --through verilog yields

[fud] ERROR: `/opt/verilator/bin/verilator --trace /tmp/tmpcsy0je3b /scratch/ad739/calyx/fud/icarus/tb.sv --binary --top-module toplevel --Mdir /tmp/tmpq176rkir -fno-inline>&2' failed:
=====STDERR=====
%Error: /tmp/tmpcsy0je3b:355:3: syntax error, unexpected wait, expecting IDENTIFIER or randomize
  355 | ) wait (
      |   ^~~~
%Error: Exiting due to 1 error(s)

=====STDOUT=====

Perhaps this kind of code should produce a Calyx error instead of a Verilator one? This way the Calyx isn't producing malformed Verilog code.

[polybeandip]

Oops, looks like there's already a file that handles these kinds issues. Adding wait (and, another one I found, break) to reserved_names.rs should do the trick. I'll make a quick PR by tonight!

[rachitnigam]

@polybeandip can you link the PR to this issue when you have one? I'm going to mark the issue stale in case there is no activity on this for a bit