[DV] reduce power_up time to 100

chiplicity · Jul 11, 2021 · 6742d3d · 6742d3d
1 parent fcab906
commit 6742d3d
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Showing 3 changed files with 3 additions and 3 deletions.
diff --git a/verilog/dv/and2/and2_tb.v b/verilog/dv/and2/and2_tb.v
@@ -28,7 +28,7 @@
 // Benchmark
 `include "and2.v"
 
-`define POWER_UP_TIME_PERIOD 200
+`define POWER_UP_TIME_PERIOD 100
 `define SOC_RESET_TIME_PERIOD 2000
 `define SOC_SETUP_TIME_PERIOD 1000*2001
 `define SOC_CLOCK_PERIOD 12.5

diff --git a/verilog/dv/ccff_test/ccff_test_tb.v b/verilog/dv/ccff_test/ccff_test_tb.v
@@ -27,7 +27,7 @@
 
 `define FPGA_BITSTREAM_SIZE 29696
 
-`define POWER_UP_TIME_PERIOD 200
+`define POWER_UP_TIME_PERIOD 100
 `define SOC_SETUP_TIME_PERIOD 2000
 `define SOC_CLOCK_PERIOD 12.5
 `define FPGA_PROG_CLOCK_PERIOD 12.5

diff --git a/verilog/dv/scff_test/scff_test_tb.v b/verilog/dv/scff_test/scff_test_tb.v
@@ -25,7 +25,7 @@
 
 `define FPGA_SCANCHAIN_SIZE 1024
 
-`define POWER_UP_TIME_PERIOD 200
+`define POWER_UP_TIME_PERIOD 100
 `define SOC_RESET_TIME_PERIOD 2000
 `define SOC_SETUP_TIME_PERIOD 200*2001
 `define SOC_CLOCK_PERIOD 12.5