Missing interface_array (follow up to PR #3101)

[hs-apotell]

For test InterfArrayBind, the uhdmtopmodules has no interface_array. PR #3101 was meant to resolve this but looks like it might be a regression.

[alaindargelas]

That is the regression: #3193

[hs-apotell]

I don't see how #3193 broke this. Neither #3101 nor #3193 had any changes to InterfArrayBind. The specific use in this test never actually worked. I reviewed the history for this log and it never had a interface_array in it.

[alaindargelas]

The interface array is bit blasted on purpose in the elaborated tree, so other objects like assign stmts can bind to the related object:

vpiInterface:
  \_interface: work@io_bus_interface (work@soc_tb.peripheral_io_bus[0]), file:dut.sv, line:14:5, endln:14:65
    |vpiParent:
    \_module: work@soc_tb (work@soc_tb), file:dut.sv, line:6:1, endln:26:10
    |vpiName:peripheral_io_bus[0]
    |vpiFullName:work@soc_tb.peripheral_io_bus[0]
    |vpiVariables:
    \_logic_var: (work@soc_tb.peripheral_io_bus[0].write_en), line:2:11, endln:2:19
      |vpiParent:
      \_interface: work@io_bus_interface (work@soc_tb.peripheral_io_bus[0]), file:dut.sv, line:14:5, endln:14:65
      |vpiTypespec:
      \_logic_typespec: , line:2:5, endln:2:10
      |vpiName:write_en
      |vpiFullName:work@soc_tb.peripheral_io_bus[0].write_en
      |vpiVisibility:1
    |vpiDefName:work@io_bus_interface
    |vpiDefFile:dut.sv
    |vpiDefLineNo:1
    |vpiInstance:
    \_module: work@soc_tb (work@soc_tb), file:dut.sv, line:6:1, endln:26:10
  |vpiInterface:
  \_interface: work@io_bus_interface (work@soc_tb.peripheral_io_bus[1]), file:dut.sv, line:14:5, endln:14:65

I didn't realize the purpose of #3101, it might create redundant information now, the bit blasted version and the array....

[hs-apotell]

I didn't realize the purpose of #3101, it might create redundant information now, the bit blasted version and the array....

It's not redundant. The array provides important information like the ranges and location. The blasted version is good for simulation but for tools, the array is needed. The instantiated modules aren't parented to the array, they are contained, referenced by the Modules container. The elements i.e. the instantiated modules are parented to the parent of the array itself, which is correct.

[hs-apotell]

To be clear #3200 doesn't address this issue. This is still open and needs to be addressed.

[hs-apotell]

@alaindargelas Did you want to take this one since you added the interface_array to the elab tree?

[alaindargelas]

Not unless it comes in the way of my work on synthesis with Surelog/Yosys, might take a while