Pyvams

Python Verilog-AMS Parser

Development Notes

After initial cloning, update submodules

  git submodule init
  git submodule update

References

• Verilog-AMS Language Reference Manual: http://accellera.org/downloads/standards/v-ams
• Pyverilog: https://github.com/PyHDI/Pyverilog