Gcd RTL example generates inferred latches

[gl387]

In the state output logic of the RTL Gcd example, the if condition is missing "else" branch, which will generate inferred latches when pushing through synthesis flow.
Specifically, if current_state == 3, then we're not writing to the outputs, resulting in inferred latches:

https://github.com/cornell-brg/pymtl/blob/master/examples/gcd/GcdUnitRTL.py#L212-L242

[cbatten]

Yep ... I noticed that too -- of course I wrote it, so I should probably fix it too :)