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72 Open 85 Closed
72 Open 85 Closed
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Issues list

possible bug in pclib/ifcs/ValRdyBundle.py
#183 opened Oct 25, 2019 by 3gx
3
Slice on fields in bitstruct does not produce valid Verilog
#179 opened Feb 11, 2019 by wizard97
sext(concat()) does not translate
#178 opened Feb 11, 2019 by wizard97
Python list slicing translation
#177 opened Jan 28, 2019 by wizard97
Help with design low-level HDL language
#171 opened Nov 16, 2018 by XVilka
Is it possible to generate sequential blocks in runtime?
#169 opened Oct 26, 2018 by zhuanhao-wu
15
will pymtl be ported to Python3
#167 opened Sep 14, 2018 by CFAndy
3
pymtl does check ".value" for single level Wire/OutPort but doesn't for the second level within message type
#162 opened Oct 20, 2016 by jsn1993
The order of test matters. I think this is a bug
#157 opened Aug 25, 2016 by jsn1993
explicit_modulename doesn't work for a very simple verilog import
#153 opened Jul 20, 2016 by jsn1993
3
Verilog translation Bits verilog_translation wontfix
#147 opened Mar 5, 2016 by Abhinav117
1
connecting wire slice to wire slice seems not to work
#144 opened Oct 30, 2015 by cbatten
2
A minor bug (or functional extensions) of range select
#143 opened Sep 18, 2015 by jsn1993
The link to the research paper in README is wrong
#142 opened Aug 28, 2015 by derekchiang
2
Verilog Translation Bug: Accessing fields from array of PortBundles not working bug verilog_translation
#141 opened Aug 27, 2015 by stevedai
PyMTL keywords bug enhancement
#140 opened Jul 21, 2015 by ss2783
Gcd RTL example generates inferred latches
#138 opened May 27, 2015 by gl387
1
Nested submodule and port list accesses do not translate correctly verilog_translation
#137 opened May 13, 2015 by dmlockhart
Imported VerilogModel wrappers won't dump *.verilator.vcd when vcd_file is set bug verilog_integration
#135 opened May 4, 2015 by dmlockhart
Verilog translated models fail if using a BitStruct defined in a non-global scope BitStructs bug verilog_translation
#133 opened Apr 16, 2015 by dmlockhart
Various checker enhancements, better Error messages enhancement
#130 opened Mar 20, 2015 by dmlockhart
Add checking to detect multiple identical assignments/multiple assignments to the same signal. enhancement verilog_translation
#127 opened Feb 20, 2015 by dmlockhart
Support s.connect() with constant Bits object Bits enhancement
#126 opened Feb 18, 2015 by cbatten
PortBundles cannot contain lists enhancement simulation verilog_translation
#125 opened Feb 16, 2015 by dmlockhart
Figure out a way to have a translatable truncate() function enhancement verilog_translation
#124 opened Feb 14, 2015 by dmlockhart
1
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