Verilog translation

[Abhinav117]

Bit slicing does not support * operation. I got the following error while translation:

pymtl.tools.translation.exceptions.VerilogTranslationError:
Slicing in behavioral blocks cannot contain arbitrary arithmetic!
Variable slices must be of the form [x:x+N] or [x:x-N]!
(and N must be constant!)

  s.cachereq_write_data_replicated0[dbw:2*dbw].value = s.cachereq_data_reg0.out

The error goes away if I declare another parameter, say dbw2, and give it the value dbw*2 beforehand.

[dmlockhart]

Supporting this functionality would require implementing a pass that could detect the multiply (or other unsupported arithmetic operation), verify the multiplied variable is a static parameter, and hoist it out of the expression to create a new parameter on the fly. This would probably be more difficulty than its worth. (Might be a fun extra credit class compiler project though.)

In the meantime, this is probably reasonable behavior (catches the problem and throws a clear error message). I would suggest closing this as "won't fix".