Slice on fields in bitstruct does not produce valid Verilog

[wizard97]

If you do

class Foo(BitStructDefinition):
    def __init__(s):
        s.dog = BitField(1)
        s.bar = BitField(8)
        s.cat = BitField(1)

Then somewhere in a model you try to do the following:

s.foo = Wire(Foo())
...
s.bob.v = s.foo.bar[:4]

This will translate to verilog as something along the lines of:

bob = foo[8:1][3:0]

Which is not valid, see:

• http://www.ece.uah.edu/~gaede/cpe526/2012%20System%20Verilog%20Language%20Reference%20Manual.pdf
• https://stackoverflow.com/questions/47813975/verilog-bit-slice-vector-twice

According to this spec in 11.4.12, this should be bob = {foo[8:1]}[3:0]. However, I was having issues with this as well. I think there should be an AST pass that does slice propogation, to turn it into bob = foo[4:1]

As is the workaround for most of these bugs, you have to manually create a temporary wire of foo.bar