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Fix AreFlagsSetToZeroCmp to not consider unsupported formats #85714

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merged 2 commits into from
May 3, 2023
Merged

Fix AreFlagsSetToZeroCmp to not consider unsupported formats #85714

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9d0f461
Fix AreFlagsSetToZeroCmp to not consider unsupported formats
tannergooding May 3, 2023
0769673
Also fix AreFlagsSetForSignJumpOpt
tannergooding May 3, 2023
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19 changes: 19 additions & 0 deletions src/coreclr/jit/emit.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1329,6 +1329,25 @@ class emitter
IS_INFO isInfo = emitGetSchedInfo(idInsFmt());
return (isInfo & (IS_AM_RW | IS_AM_WR)) != 0;
}

bool idHasMem() const
{
return idHasMemGen()
|| idHasMemStk()
|| idHasMemAdr();
}
bool idHasMemRead() const
{
return idHasMemGenRead()
|| idHasMemStkRead()
|| idHasMemAdrRead();
}
bool idHasMemWrite() const
{
return idHasMemGenWrite()
|| idHasMemStkWrite()
|| idHasMemAdrWrite();
}
#endif // defined(TARGET_XARCH)
#ifdef TARGET_ARMARCH
insOpts idInsOpt() const
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15 changes: 12 additions & 3 deletions src/coreclr/jit/emitxarch.cpp
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Expand Up @@ -887,21 +887,30 @@ bool emitter::AreFlagsSetToZeroCmp(regNumber reg, emitAttr opSize, GenCondition
return false;
}

// Only consider if safe
//
if (!emitCanPeepholeLastIns())
{
// Don't consider if not safe
return false;
}

instrDesc* id = emitLastIns;
instruction lastIns = id->idIns();

if (!id->idHasReg1() || (id->idReg1() != reg))
if (!id->idIsReg1Write() || (id->idReg1() != reg))
{
// Don't consider instructions which didn't write a register
return false;
}

if (id->idHasMemWrite() || id->idIsReg2Write())
{
// Don't consider instructions which also wrote a mem location or second register
return false;
}
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This is more conservative than it needs to be but brings it back inline with what was previously being checked:

    switch (fmt)
    {
        case IF_RWR_CNS:
        case IF_RRW_CNS:
        case IF_RRW_SHF:
        case IF_RWR_RRD:
        case IF_RRW_RRD:
        case IF_RWR_MRD:
        case IF_RWR_SRD:
        case IF_RRW_SRD:
        case IF_RWR_ARD:
        case IF_RRW_ARD:
        case IF_RWR:
        case IF_RRD:
        case IF_RRW:
        case IF_RWR_RRD_RRD:
        case IF_RWR_RRD_MRD:
        case IF_RWR_RRD_ARD:
        case IF_RWR_RRD_SRD:
            break;
        default:
            return false;
    }

The general issue was that the check missed cases like xadd which wrote two registers or a mem location + a register and while that isn't "incorrect" to do, handling it would require more checks to ensure the correct register write impacted the flags.

I opted for the faster/more conservative fix and will log an issue tracking adding the correctly handling for cases like xadd


assert(!id->idIsReg3Write());
assert(!id->idIsReg4Write());

// Certain instruction like and, or and xor modifies exactly same flags
// as "test" instruction.
// They reset OF and CF to 0 and modifies SF, ZF and PF.
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