Multiple FPGA/CPLD designs
- Please start with the gates/doc/how-to-build-enivronment.md document.
- Then look at the gates/led-blink project. Use this as a pipe-flush to sort out your ISE install and JTAG burn process.
- All of the other stuff in the gates folder is currently WIP.
- Next module to be completed is a UART hello-world. So that we can have output for debug.
- After that is a 4KHz SDIO card read to UART dump, via button push for sector advance. Where sector data will be analyzed vs the raw image file that was written to the uSD card, bad block detection will be investiagted.
- Then comes a 4 bit SDIO block burst write test with raw image analysis.
- Finally the 40 pin data capture can be dumped as an SDIO block burst to the uSD card.