Add aarch32 support

[jonathanpallant]

Implements the sysreg calls for aarch32 and aarch64.

Also fixes an issue I observed where SPECIAL_SECURE was being withheld from the application, but not SPECIAL_NONE - that seemed wrong.

See https://github.com/ferrous-systems/cortex-r/blob/send-arm-gic-upstream/cortex-r-examples/src/bin/gic.rs for an example tested in QEMU:

$ criticalup run cargo run --bin gic --features=gic --target=armv8r-none-eabihf
   Compiling cortex-r-examples v0.1.0 (/Users/jonathan/Documents/ferrous-systems/demos/embedded-world-2025/cortex-r/cortex-r-examples)
   Compiling arm-gic v0.1.2 (https://github.com/jonathanpallant/arm-gic.git?rev=4b7fb201707be062546148bc5c4b70b08c8c0455#4b7fb201)
    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.49s
     Running `qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -kernel /Users/jonathan/Documents/ferrous-systems/demos/embedded-world-2025/cortex-r/target/armv8r-none-eabihf/debug/gic`
Found PERIPHBASE 0xf0000000
Creating GIC driver @ 0xf0000000 / 0xf0100000
Calling git.setup()
Configure SGI
gic.enable_interrupt()
Enabling interrupts...
CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=0x1f }
CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=0x1f }
Send SGI
> IRQ
- IRQ handle SGI 3
< IRQ

I'm using Ferrocene (criticalup run) because upstream Rust has armv8r-none-eabihf at Tier 3 so it isn't in rustup. But also because I can.

[google-cla]

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[jonathanpallant]

BRB, talking to my legal team about the CLA.

[jonathanpallant]

oops, I forgot fake.rs. Tests should now pass.

[jonathanpallant]

The multi-core PR got merged and I need to rebase. Unfortunately that PR didn't update the example in lib.rs so I don't really know what I need to change in my application.

[qwandor]

The multi-core PR got merged and I need to rebase. Unfortunately that PR didn't update the example in lib.rs so I don't really know what I need to change in my application.

Ah sorry, we don't have doc tests running so I missed that. I'll send a PR to fix it, but it if you're on a single-core system it should just be a matter of passing 0 in a bunch of places.

[jonathanpallant]

Rebased and re-tested.

If you don't get it right, you get a panic :/. But at least that told me that SGIs are in fact private interrupts (which makes sense). A compile failure would be better but I can't immediately think how to do that - you would probably have to split the interrupt type into private and shared kinds.

[jonathanpallant]

rebased on main

[qwandor]

Thanks for rebasing. I'll look at this once the CLA is sorted.

[jonathanpallant]

The CLA is signed - just waiting for it to process.

[qwandor]

The CLA is signed - just waiting for it to process.

Hi Jonathan, your CLA signature still isn't showing up, either against your GitHub username or your email address jonathan.pallant@ferrous-systems.com. Did you maybe make a typo entering your GitHub username when you signed it?

[jonathanpallant]

We have signed it as a Corporation, and I am a member of the google-cla@ferrous-systems.com group.

[qwandor]

Ah, gotcha. Hopefully that gets processed soon then.

[jonathanpallant]

tada

[qwandor]

Thanks!