DSLX DMA: Implement FIFO and CSR

[mczyz-antmicro]

DSLX DMA

This PR implements modules needed to build the DSLX DMA as described in issue #1208.

Ready for review

TODO:

• DSLX design and test
  • Main Controller
    • Address Generator
      • Based on CSR configuration, it produces a list of addresses
      • Passes Unit test
      • Control channels are integrated with top-level
    • Frontend Reader
      • Based on incoming addresses, it creates AXI-"like" transactions
      • Transactions can be longer than 1
      • Control channels are integrated with top-level
    • Frontend Writer
      • Based on incoming addresses, it creates AXI-"like" transactions
      • Transactions can be longer than 1
      • Control channels are integrated with top-level
    • Interrupt Controller
      • Expose Single Value Channels Expose Single Value Channels in DSLX frontend #1281
  • Integration
    • Test: Address Generators, CSRs, Frontends, GPF
    • Add FIFOs to test
  • CSR
    • AXI Write Transaction (Data Width = 32, Transaction Length = 1) results in write to selected register
    • AXI Read Transaction (Data Width = 32, Transaction Length = 1) results in read from selected register
    • Address selected in the AXI RW Transaction is divided/multiplied by 4. (Linux driver calculates address in bytes)
    • Number and width of registers is parametrizable, but set to 14x32bits as in the FastVDMA project
    • CSRs are correctly decoded and affect the state of the main controller
      • Control Register
        • Writer start and Reader start bit
          • Information is passed to the Address Generator
          • Bit resets itself unless in loop mode
        • Writer sync disable and Reader sync disable
          • Synchronization to external signal
        • Writer loop mode and Reader loop mode
          • run frontend transfers in a loop
      • Status Register
        • Writer busy and Reader busy bit
          • Reads as 1 while frontend is busy with transfers
      • Interrupt Mask Register
        • Writer mask and Reader mask bit
          • Enables R/W interrupt
      • Interrupt Status Register
        • Writer interrupt and Reader interrupt
          • Reads as 1 when interrupt has occurred (done)
          • Write 1 to clear interrupt
      • Reader Start Address Register
      • Reader line length Register
      • Reader line count Register
      • Reader stride between lines Register
      • Writer start address Register
      • Writer line length Register
      • Writer line count Register
      • Writer stride between lines Register
      • Version Register
        • DMA Version can be read from this register
      • Configuration Register
        • Different frontends can be selected
  • FIFO
    • AXI Stream write (Transaction Length = 1) is correctly written to RAM at last free memory location
    • AXI Stream read (Transaction Length = 1) is correctly read from RAM and memory location is freed
    • FIFO of length L correctly handles N transactions when N >> L (overflow condition)
    • Debug integration test (2 FIFOs connected via GPF) DSLX: Order of expressions breaks tests; RAM hangs #1237
  • Mock Generic Physical Function
    • Increment mode (all payloads are incremented by 1)
    • Invert mode (all payloads are negated and truncated to 1byte)
    • Used to test top-level view
• RTL Benchmark
  • Verilog generation
    • CSR
    • AXI CSR
    • Frontend writer
    • Frontend reader
    • Address Generator
    • TBD (other blocks)
  • Frequency, power, area estimation
    • TBD

Implementation details

See README.md included in this PR for implementation details

Limitations

Current CI configuration fails:

• Bazel BUILD failed on an issue unrelated to this PR

WARNING: Download from https://mirror.bazel.build/repo1.maven.org/maven2/com/google/guava/guava/32.1.1-jre/guava-32.1.1-jre.jar failed: class java.io.FileNotFoundException GET returned 404 Not Found

• Main Controller Test fails with "DEADLINE_EXCEEDED" error due to the same issue as I had reported in DSLX: Order of expressions breaks tests; RAM hangs #1237. If you uncomment the last proc in the main_controller.x file, then the test passes. There are also other tests of the main controller that work standalone, but fail once at least 2 procs are uncommented
• AXI CSR IR optimization fails on "UNIMPLEMENTED" error. Please review BUILD rules and advise whether I should change BUILD rules or this feature will be implemented and we can proceed with merging this PR

[proppy]

@rw1nkler suggested that could also be a good standalone thing to review and land soonish.

[proppy]

@hongted mentioned that @grebe might be interested to look at the fifo implementation in that PR:
https://github.com/google/xls/pull/1215/files#diff-e139db19aacd0f9c2a28123c053722349c6ef5ba135d288f53b92797112614dd

[mczyz-antmicro]

@proppy I agree, PR is ready for review. I force pushed today to include last changes and GH workflows.

[proppy]

can we inline those actions in a dedicated zstd workflow for now? (and maybe later have a separate PR for refactoring the existing workflows w/ composite actions); I agree that we could have a better architecture of our workflows (maybe we could have a separate https://github.com/google/xls/issues/new?template=enhancement-proposal.yml for this?) but I think that it's orthogonal to the work being review here.

[mczyz-antmicro]

I updated the workflows to create a simpler, flat configuration. If you wish to review the artifacts: https://github.com/antmicro/xls/actions/runs/8551896740