Merge pull request #4 from fritzbauer/CycloneVPLL

Cyclone V using altera_pll

gateware/car.py

@@ -156,6 +156,86 @@ def elaborate(self, platform):
 
         return m
 
+
+class IntelCycloneVFPGAClockDomainGenerator(Elaboratable, ClockDomainGeneratorBase):
+
+    def __init__(self, *, clock_frequencies=None, clock_signal_name=None):
+        pass
+
+    def elaborate(self, platform):
+        m = Module()
+
+        # Create our domains
+        # usb: USB clock: 60MHz
+        # adat: ADAT clock = 12.288 MHz = 48 kHz * 256
+        # dac: I2S DAC clock 48k = 3.072 MHz = 48 kHz * 32 bit * 2 channels
+        # sync: ADAT transmit domain clock = 61.44 MHz = 48 kHz * 256 * 5 output terminals
+        # fast: ADAT sampling clock = 98.304 MHz = 48 kHz * 256 * 8 times oversampling
+        m.domains.usb  = ClockDomain("usb")
+        m.domains.sync = ClockDomain("sync")
+        m.domains.fast = ClockDomain("fast")
+        m.domains.adat = ClockDomain("adat")
+        m.domains.dac  = ClockDomain("dac")
+
+        clk = platform.request(platform.default_clk)
+
+        main_clock    = Signal()
+        audio_clocks  = Signal(4)
+
+        sys_locked    = Signal()
+        audio_locked  = Signal()
+
+        reset         = Signal()
+
+        m.submodules.mainpll = Instance("altera_pll",
+            p_pll_type="General",
+            p_pll_subtype="General",
+            p_fractional_vco_multiplier="false",
+            p_operation_mode="normal",
+            p_reference_clock_frequency="50.0 MHz",
+            p_number_of_clocks="1",
+
+            p_output_clock_frequency0="60.000000 MHz",
+
+
+            # Drive our clock from the internal 50MHz clock
+            i_refclk = clk,
+            o_outclk = main_clock,
+            o_locked = sys_locked
+        )
+
+        m.submodules.audiopll = Instance("altera_pll",
+            p_pll_type="General",
+            p_pll_subtype="General",
+            p_fractional_vco_multiplier="true",
+            p_operation_mode="normal",
+            p_reference_clock_frequency="60.0 MHz",
+            p_number_of_clocks="4",
+
+            p_output_clock_frequency0="12.288000 MHz",
+            p_output_clock_frequency1="3.072000 MHz",
+            p_output_clock_frequency2="61.440000 MHz",
+            p_output_clock_frequency3="98.304000 MHz",
+
+            # Drive our clock from the mainpll
+            i_refclk=main_clock,
+            o_outclk=audio_clocks,
+            o_locked=audio_locked
+        )
+
+        m.d.comb += [
+            reset.eq(~(sys_locked & audio_locked)),
+            ClockSignal("usb") .eq(main_clock),
+            ClockSignal("adat").eq(audio_clocks[0]),
+            ClockSignal("dac").eq(audio_clocks[1]),
+            ClockSignal("sync").eq(audio_clocks[2]),
+            ClockSignal("fast").eq(audio_clocks[3])
+        ]
+
+        self.wire_up_reset(m, reset)
+
+        return m
+
 class Xilinx7SeriesClockDomainGenerator(Elaboratable, ClockDomainGeneratorBase):
     ADAT_DIV_48k    = 83
     ADAT_MULT_48k   = 17

gateware/platforms.py

@@ -9,7 +9,7 @@
 
 from luna.gateware.platform.core import LUNAPlatform
 
-from car                     import IntelFPGAClockDomainGenerator, Xilinx7SeriesClockDomainGenerator
+from car                     import IntelFPGAClockDomainGenerator, IntelCycloneVFPGAClockDomainGenerator, Xilinx7SeriesClockDomainGenerator
 from adatface_rev0_baseboard import ADATFaceRev0Baseboard
 
 class IntelFPGAParameters:
@@ -34,7 +34,7 @@ class IntelFPGAParameters:
 
 class ADATFaceCycloneV(QMTech5CEFA2Platform, LUNAPlatform):
     fast_multiplier        = 9
-    clock_domain_generator = IntelFPGAClockDomainGenerator
+    clock_domain_generator = IntelCycloneVFPGAClockDomainGenerator
     fast_domain_clock_freq = int(48e3 * 256 * fast_multiplier)
 
     @property