icedland · wtfsck · Feb 23, 2022 · Feb 23, 2022 · Feb 23, 2022
diff --git a/src/UnitTests/Intel/Encoder/OpCodeInfos.txt b/src/UnitTests/Intel/Encoder/OpCodeInfos.txt
@@ -4836,3 +4836,4 @@ Xstore_alt_64, Xstore_alt, Unknown, Unknown, legacy, F3, 0F, A7F8, a64 F3 0F A7
 Xsha512_alt_16, Xsha512_alt, Unknown, Unknown, legacy, F3, 0F, A6D8, a16 F3 0F A6 D8, XSHA512_ALT, 16 32 cpl0 cpl1 cpl2 cpl3 a16 intel16 intel32 amd16 amd32 rm pm v86 cm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
 Xsha512_alt_32, Xsha512_alt, Unknown, Unknown, legacy, F3, 0F, A6D8, a32 F3 0F A6 D8, XSHA512_ALT, 16 32 64 cpl0 cpl1 cpl2 cpl3 a32 intel16 intel32 intel64 amd16 amd32 amd64 rm pm v86 cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
 Xsha512_alt_64, Xsha512_alt, Unknown, Unknown, legacy, F3, 0F, A6D8, a64 F3 0F A6 D8, XSHA512_ALT, 64 cpl0 cpl1 cpl2 cpl3 a64 intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
+Zero_bytes, Zero_bytes, Unknown, Unknown, legacy, , legacy, 00, <zero_bytes>, ZERO_BYTES, no-instr 16 32 64 cpl0 cpl1 cpl2 cpl3 intel16 intel32 intel64 amd16 amd32 amd64 rm pm v86 cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
diff --git a/src/UnitTests/Intel/Formatter/Fast/Test16_NonDec_Default.txt b/src/UnitTests/Intel/Formatter/Fast/Test16_NonDec_Default.txt
@@ -22,6 +22,7 @@ fstsw fs:[bx+si]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 77h
 db 77h,0A9h
 db 77h,0A9h,0CEh

diff --git a/src/UnitTests/Intel/Formatter/Fast/Test16_NonDec_Inverted.txt b/src/UnitTests/Intel/Formatter/Fast/Test16_NonDec_Inverted.txt
@@ -22,6 +22,7 @@ fstsw word ptr fs:[bx+si]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 0x77
 db 0x77, 0xa9
 db 0x77, 0xa9, 0xce

diff --git a/src/UnitTests/Intel/Formatter/Fast/Test32_NonDec_Default.txt b/src/UnitTests/Intel/Formatter/Fast/Test32_NonDec_Default.txt
@@ -22,6 +22,7 @@ fstsw fs:[eax]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 77h
 db 77h,0A9h
 db 77h,0A9h,0CEh

diff --git a/src/UnitTests/Intel/Formatter/Fast/Test32_NonDec_Inverted.txt b/src/UnitTests/Intel/Formatter/Fast/Test32_NonDec_Inverted.txt
@@ -22,6 +22,7 @@ fstsw word ptr fs:[eax]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 0x77
 db 0x77, 0xa9
 db 0x77, 0xa9, 0xce

diff --git a/src/UnitTests/Intel/Formatter/Fast/Test64_NonDec_Default.txt b/src/UnitTests/Intel/Formatter/Fast/Test64_NonDec_Default.txt
@@ -19,6 +19,7 @@ fsave fpustate108 ptr fs:[rax]
 fstsw [rax]
 fstsw fs:[rax]
 fstsw ax
+zero_bytes
 db 77h
 db 77h,0A9h
 db 77h,0A9h,0CEh

diff --git a/src/UnitTests/Intel/Formatter/Fast/Test64_NonDec_Inverted.txt b/src/UnitTests/Intel/Formatter/Fast/Test64_NonDec_Inverted.txt
@@ -19,6 +19,7 @@ fsave fpustate108 ptr fs:[rax]
 fstsw word ptr ds:[rax]
 fstsw word ptr fs:[rax]
 fstsw ax
+zero_bytes
 db 0x77
 db 0x77, 0xa9
 db 0x77, 0xa9, 0xce

diff --git a/src/UnitTests/Intel/Formatter/Gas/Test16_NonDec_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test16_NonDec_ForceSuffix.txt
@@ -22,6 +22,7 @@ fstsww fs:(bx,si)
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 .byte 0x77
 .byte 0x77, -0x57
 .byte 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/Formatter/Gas/Test16_NonDec_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test16_NonDec_NoSuffix.txt
@@ -22,6 +22,7 @@ fstsw %fs:(%bx, %si)
 fstsw %ax
 fstdw %ax
 fstsg %ax
+zero_bytes
 .byte 0x77
 .byte 0x77,0xa9
 .byte 0x77,0xa9,0xce

diff --git a/src/UnitTests/Intel/Formatter/Gas/Test32_NonDec_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test32_NonDec_ForceSuffix.txt
@@ -22,6 +22,7 @@ fstsww fs:(eax)
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 .byte 0x77
 .byte 0x77, -0x57
 .byte 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/Formatter/Gas/Test32_NonDec_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test32_NonDec_NoSuffix.txt
@@ -22,6 +22,7 @@ fstsw %fs:(%eax)
 fstsw %ax
 fstdw %ax
 fstsg %ax
+zero_bytes
 .byte 0x77
 .byte 0x77,0xa9
 .byte 0x77,0xa9,0xce

diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_NonDec_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_NonDec_ForceSuffix.txt
@@ -19,6 +19,7 @@ fsavel fs:(rax)
 fstsww (rax)
 fstsww fs:(rax)
 fstsw ax
+zero_bytes
 .byte 0x77
 .byte 0x77, -0x57
 .byte 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_NonDec_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_NonDec_NoSuffix.txt
@@ -19,6 +19,7 @@ fsave %fs:(%rax)
 fstsw (%rax)
 fstsw %fs:(%rax)
 fstsw %ax
+zero_bytes
 .byte 0x77
 .byte 0x77,0xa9
 .byte 0x77,0xa9,0xce

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test16_NonDec_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test16_NonDec_MemAlways.txt
@@ -22,6 +22,7 @@ fstsw word ptr fs:[bx+si]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 0x77
 db 0x77, -0x57
 db 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test16_NonDec_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test16_NonDec_MemDefault.txt
@@ -22,6 +22,7 @@ fstsw fs:[bx+si]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 0x77
 db 0x77,0xa9
 db 0x77,0xa9,0xce

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test16_NonDec_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test16_NonDec_MemMinimum.txt
@@ -22,6 +22,7 @@ fstsw fs:[bx+si]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 0x77
 db 0x77, -0x57
 db 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test32_NonDec_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test32_NonDec_MemAlways.txt
@@ -22,6 +22,7 @@ fstsw word ptr fs:[eax]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 0x77
 db 0x77, -0x57
 db 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test32_NonDec_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test32_NonDec_MemDefault.txt
@@ -22,6 +22,7 @@ fstsw fs:[eax]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 0x77
 db 0x77,0xa9
 db 0x77,0xa9,0xce

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test32_NonDec_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test32_NonDec_MemMinimum.txt
@@ -22,6 +22,7 @@ fstsw fs:[eax]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 0x77
 db 0x77, -0x57
 db 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_NonDec_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_NonDec_MemAlways.txt
@@ -19,6 +19,7 @@ fsave fs:[rax]
 fstsw word ptr [rax]
 fstsw word ptr fs:[rax]
 fstsw ax
+zero_bytes
 db 0x77
 db 0x77, -0x57
 db 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_NonDec_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_NonDec_MemDefault.txt
@@ -19,6 +19,7 @@ fsave fs:[rax]
 fstsw [rax]
 fstsw fs:[rax]
 fstsw ax
+zero_bytes
 db 0x77
 db 0x77,0xa9
 db 0x77,0xa9,0xce

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_NonDec_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_NonDec_MemMinimum.txt
@@ -19,6 +19,7 @@ fsave fs:[rax]
 fstsw [rax]
 fstsw fs:[rax]
 fstsw ax
+zero_bytes
 db 0x77
 db 0x77, -0x57
 db 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/Formatter/Masm/Test16_NonDec_MemAlways.txt b/src/UnitTests/Intel/Formatter/Masm/Test16_NonDec_MemAlways.txt
@@ -22,6 +22,7 @@ fstsw word ptr fs:[bx+si]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 77h
 db 77h, -57h
 db 77h, -57h, -32h

diff --git a/src/UnitTests/Intel/Formatter/Masm/Test16_NonDec_MemDefault.txt b/src/UnitTests/Intel/Formatter/Masm/Test16_NonDec_MemDefault.txt
@@ -22,6 +22,7 @@ fstsw fs:[bx+si]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 77h
 db 77h,0A9h
 db 77h,0A9h,0CEh

diff --git a/src/UnitTests/Intel/Formatter/Masm/Test16_NonDec_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Masm/Test16_NonDec_MemMinimum.txt
@@ -22,6 +22,7 @@ fstsw fs:[bx+si]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 77h
 db 77h, -57h
 db 77h, -57h, -32h

diff --git a/src/UnitTests/Intel/Formatter/Masm/Test32_NonDec_MemAlways.txt b/src/UnitTests/Intel/Formatter/Masm/Test32_NonDec_MemAlways.txt
@@ -22,6 +22,7 @@ fstsw word ptr fs:[eax]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 77h
 db 77h, -57h
 db 77h, -57h, -32h

diff --git a/src/UnitTests/Intel/Formatter/Masm/Test32_NonDec_MemDefault.txt b/src/UnitTests/Intel/Formatter/Masm/Test32_NonDec_MemDefault.txt
@@ -22,6 +22,7 @@ fstsw fs:[eax]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 77h
 db 77h,0A9h
 db 77h,0A9h,0CEh

diff --git a/src/UnitTests/Intel/Formatter/Masm/Test32_NonDec_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Masm/Test32_NonDec_MemMinimum.txt
@@ -22,6 +22,7 @@ fstsw fs:[eax]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 77h
 db 77h, -57h
 db 77h, -57h, -32h

diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_NonDec_MemAlways.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_NonDec_MemAlways.txt
@@ -19,6 +19,7 @@ fsave fs:[rax]
 fstsw word ptr [rax]
 fstsw word ptr fs:[rax]
 fstsw ax
+zero_bytes
 db 77h
 db 77h, -57h
 db 77h, -57h, -32h

diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_NonDec_MemDefault.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_NonDec_MemDefault.txt
@@ -19,6 +19,7 @@ fsave fs:[rax]
 fstsw [rax]
 fstsw fs:[rax]
 fstsw ax
+zero_bytes
 db 77h
 db 77h,0A9h
 db 77h,0A9h,0CEh

diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_NonDec_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_NonDec_MemMinimum.txt
@@ -19,6 +19,7 @@ fsave fs:[rax]
 fstsw [rax]
 fstsw fs:[rax]
 fstsw ax
+zero_bytes
 db 77h
 db 77h, -57h
 db 77h, -57h, -32h

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test16_NonDec_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test16_NonDec_MemAlways.txt
@@ -22,6 +22,7 @@ fstsw word [fs:bx+si]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 0x77
 db 0x77, -0x57
 db 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test16_NonDec_MemDefault.txt b/src/UnitTests/Intel/Formatter/Nasm/Test16_NonDec_MemDefault.txt
@@ -22,6 +22,7 @@ fstsw [fs:bx+si]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 0x77
 db 0x77,0xa9
 db 0x77,0xa9,0xce

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test16_NonDec_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test16_NonDec_MemMinimum.txt
@@ -22,6 +22,7 @@ fstsw [fs:bx+si]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 0x77
 db 0x77, -0x57
 db 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test32_NonDec_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test32_NonDec_MemAlways.txt
@@ -22,6 +22,7 @@ fstsw word [fs:eax]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 0x77
 db 0x77, -0x57
 db 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test32_NonDec_MemDefault.txt b/src/UnitTests/Intel/Formatter/Nasm/Test32_NonDec_MemDefault.txt
@@ -22,6 +22,7 @@ fstsw [fs:eax]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 0x77
 db 0x77,0xa9
 db 0x77,0xa9,0xce

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test32_NonDec_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test32_NonDec_MemMinimum.txt
@@ -22,6 +22,7 @@ fstsw [fs:eax]
 fstsw ax
 fstdw ax
 fstsg ax
+zero_bytes
 db 0x77
 db 0x77, -0x57
 db 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_NonDec_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_NonDec_MemAlways.txt
@@ -19,6 +19,7 @@ fsave [fs:rax]
 fstsw word [rax]
 fstsw word [fs:rax]
 fstsw ax
+zero_bytes
 db 0x77
 db 0x77, -0x57
 db 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_NonDec_MemDefault.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_NonDec_MemDefault.txt
@@ -19,6 +19,7 @@ fsave [fs:rax]
 fstsw [rax]
 fstsw [fs:rax]
 fstsw ax
+zero_bytes
 db 0x77
 db 0x77,0xa9
 db 0x77,0xa9,0xce

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_NonDec_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_NonDec_MemMinimum.txt
@@ -19,6 +19,7 @@ fsave [fs:rax]
 fstsw [rax]
 fstsw [fs:rax]
 fstsw ax
+zero_bytes
 db 0x77
 db 0x77, -0x57
 db 0x77, -0x57, -0x32

diff --git a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt
@@ -22005,3 +22005,5 @@ F3 0FA7 F8, Xstore_alt_64, Legacy, PADLOCK_RNG, cwm=es:rdi;Unknown cr=rdi cw=rdi
 67 F3 0FA6 D8, Xsha512_alt_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=esi;edi cw=rsi r=ecx cw=rcx
 # rep xsha512_alt
 F3 0FA6 D8, Xsha512_alt_64, Legacy, PADLOCK_PHE, crm=es:rdi;Unknown cwm=es:rdi;Unknown crm=es:rsi;Unknown cr=rsi;rdi cw=rsi rcw=rcx
+# zero_bytes
+, Zero_bytes, Legacy, INTEL8086, special
diff --git a/src/csharp/Intel/Generator/Enums/Code.cs b/src/csharp/Intel/Generator/Enums/Code.cs
@@ -4844,6 +4844,8 @@ enum Code {
 		Xsha512_alt_16,
 		Xsha512_alt_32,
 		Xsha512_alt_64,
+		[Comment("A zero-sized instruction. Can be used as a label.")]
+		Zero_bytes,
 	}
 
 	[TypeGen(TypeGenOrders.CreatedInstructions)]

diff --git a/src/csharp/Intel/Generator/Enums/Mnemonic.cs b/src/csharp/Intel/Generator/Enums/Mnemonic.cs
@@ -1841,5 +1841,6 @@ enum Mnemonic {
 		Xsha512,
 		Xstore_alt,
 		Xsha512_alt,
+		Zero_bytes,
 	}
 }
diff --git a/src/csharp/Intel/Generator/Tables/InstructionDefs.txt b/src/csharp/Intel/Generator/Tables/InstructionDefs.txt
@@ -56,6 +56,11 @@ INSTRUCTION: <dq> | <dq> | INTEL8086
 	nasm: decl
 END
 
+# Code: Zero_bytes
+INSTRUCTION: <zero_bytes> | ZERO_BYTES | INTEL8086
+	flags: no-instr
+END
+
 # Code: Add_rm8_r8
 INSTRUCTION: 00 /r | ADD r/m8, r8 | INTEL8086
 	ops: rw=rm r=reg | UInt8

diff --git a/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests16.g.cs b/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests16.g.cs
@@ -46977,6 +46977,11 @@ public void xtest() {
 			TestAssembler(c => c.xtest(), Instruction.Create(Code.Xtest));
 		}
 
+		[Fact]
+		public void zero_bytes() {
+			TestAssembler(c => c.zero_bytes(), Instruction.Create(Code.Zero_bytes));
+		}
+
 	}
 }
 #endif
diff --git a/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests32.g.cs b/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests32.g.cs
@@ -47184,6 +47184,11 @@ public void xtest() {
 			TestAssembler(c => c.xtest(), Instruction.Create(Code.Xtest));
 		}
 
+		[Fact]
+		public void zero_bytes() {
+			TestAssembler(c => c.zero_bytes(), Instruction.Create(Code.Zero_bytes));
+		}
+
 	}
 }
 #endif