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Achievements

Achievement: QuickdrawAchievement: YOLOAchievement: Pull Sharkx2Achievement: Starstruck

Highlights

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Organizations

@AUCOHL @AUTOPIA-OS

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kanndil/README.md

header

I'm Youssef Kandil (Kanndil)

I'm a Research Assistant and a Computer Engineering graduate from The American University in Cairo. My primary interests lie in Hardware Design, Embedded Systems, and Tiny Machine Learning. As a member of the AUC Open Source Hardware Lab AUC Open Source Hardware Lab (AUCOHL), I actively contribute to projects aimed at enhancing power efficiency and performance in computing systems.

Projects

Here are some of my key projects:

  • ❄️ Lighter ❄️: An automatic clock gating utility. Dynamic power reduction tool for open-source standard cell libraries. Check it out

  • 🧪 PODEM-ATPG 🧪: A Google Summer of Code 2024 (GSOC2024) project, focused on implementing the Path-Oriented Decision Making (PODEM) algorithm for Automatic Test Pattern Generation (ATPG). Check it out

  • 🏎️ AUTOPIA 🏎️: My Bachelor's thesis project in collaboration with Siemens. An AUTOSAR-compliant MultiCore Operating System. Check it out

  • 🎧 KWS MFCC Optimizer 🎧: Enhancing the Mel-Frequency Cepstral Coefficients algorithm for efficient embedded audio machine learning applications. Check it out

📫 How to reach me

Work Email: youssef.kandil@efabless.com

Personal Email: youssefkandil@aucegypt.edu

Quick Overview 📈

kanndil's Contribution kanndil's Rating


Connect with me

ykanndil youssef-kandil-195638216

Pinned Loading

  1. AUCOHL/Lighter AUCOHL/Lighter Public

    An automatic clock gating utility

    Verilog 40 5

  2. AUTOPIA-OS/MultiCore-OS AUTOPIA-OS/MultiCore-OS Public

    C 8 1

  3. PathView PathView Public

    An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.

    HTML 2 1

  4. detr-tensorflow detr-tensorflow Public

    Forked from Visual-Behavior/detr-tensorflow

    Tensorflow implementation of DETR : Object Detection with Transformers

    Jupyter Notebook

  5. chipsalliance/yosys-f4pga-plugins chipsalliance/yosys-f4pga-plugins Public

    Plugins for Yosys developed as part of the F4PGA project.

    Verilog 81 46

  6. PodemQuest PodemQuest Public

    Path-Oriented Decision Making (PODEM) algorithm for Automatic Test Pattern Generation (ATPG).

    Python