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[DAG] Add knownbits/signbits handling for ISD::AVG* nodes #53622

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RKSimon opened this issue Feb 7, 2022 · 3 comments · Fixed by #86754 or #76644
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[DAG] Add knownbits/signbits handling for ISD::AVG* nodes #53622

RKSimon opened this issue Feb 7, 2022 · 3 comments · Fixed by #86754 or #76644
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RKSimon commented Feb 7, 2022

https://reviews.llvm.org/D106237 adds the ISD::AVGFLOORS/AVGFLOORU/AVGCEILS/AVGCEILU nodes which we will require value tracking handling for in SelectionDAG.

CC @davemgreen
@RKSimon RKSimon self-assigned this Feb 8, 2022
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RKSimon commented Feb 12, 2022

ISD::AVGCEILU handling - https://reviews.llvm.org/D119629

@RKSimon RKSimon mentioned this issue Feb 16, 2022
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@RKSimon RKSimon removed their assignment May 3, 2022
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I can take this as well

@snikitav snikitav mentioned this issue Dec 31, 2023
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@snikitav snikitav mentioned this issue Mar 27, 2024
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@RKSimon RKSimon reopened this Apr 2, 2024
davemgreen pushed a commit that referenced this issue Apr 6, 2024
@snikitav
[AArch64] SimplifyDemandedBitsForTargetNode - add AArch64ISD::BICi ha…
d38bff4 
…ndling (#76644)

Fold BICi if all destination bits are already known to be zeroes

```llvm
define <8 x i16> @haddu_known(<8 x i8> %a0, <8 x i8> %a1) {
  %x0 = zext <8 x i8> %a0 to <8 x i16>
  %x1 = zext <8 x i8> %a1 to <8 x i16>
  %hadd = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
  %res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511,i16 511, i16 511, i16 511, i16 511>
  ret <8 x i16> %res
}
declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)
```

```
haddu_known:                            // @haddu_known
        ushll   v0.8h, v0.8b, #0
        ushll   v1.8h, v1.8b, #0
        uhadd   v0.8h, v0.8h, v1.8h
        bic     v0.8h, #254, lsl #8 <-- this one will be removed as we know high bits are zero extended
        ret
```

Fixes #53881
Fixes #53622
@EugeneZelenko EugeneZelenko added backend:AArch64 and removed llvm:SelectionDAG SelectionDAGISel as well labels Apr 6, 2024
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llvmbot commented Apr 6, 2024

@llvm/issue-subscribers-backend-aarch64

Author: Simon Pilgrim (RKSimon)

https://reviews.llvm.org/D106237 adds the ISD::AVGFLOORS/AVGFLOORU/AVGCEILS/AVGCEILU nodes which we will require value tracking handling for in SelectionDAG.

CC @davemgreen

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