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RISCV vector zvl256b miscompile at -O2 #82430
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@llvm/issue-subscribers-backend-risc-v Author: Patrick O'Neill (patrick-rivos)
Testcase:
```c
int printf(const char *, ...);
int c;
int d[10][10];
char e, f;
int main() {
for (f = 0; f < 8; f += 1) {
--c >> d[0][4] && (e = 0);
d[0][4] = d[5][0];
}
printf("%X\n", d[0][4]);
}
```
Commands: > /scratch/tc-testing/tc-feb-20-llvm/build/bin/clang -march=rv64gcv_zvl256b -O2 red.c -o red.out
> /scratch/tc-testing/tc-feb-20-llvm/build/bin/qemu-riscv64 red.out
AB2B8CB8
> /scratch/tc-testing/tc-feb-20-llvm/build/bin/clang -march=rv64gcv_zvl256b -O2 red.c -o red.out -fuse-ld=lld
> /scratch/tc-testing/tc-feb-20-llvm/build/bin/qemu-riscv64 red.out
555599E0
> /scratch/tc-testing/tc-feb-20-llvm/build/bin/clang red.c -o red.out
> /scratch/tc-testing/tc-feb-20-llvm/build/bin/qemu-riscv64 red.out
0 Bugpoint, ASM, red.c: c-asm-bc.zip
Discovered/tested using 7f3980a (not bisected) |
This could mean either the SLP vectorizer generated bad code. Or the SLP IR is good but SelectionDAG miscompiled it. |
This part is really weird, the use of different linkers results in different outputs:
I don't see any assemblies diff: https://godbolt.org/z/8Thfqq9M7. |
This address doesn't make sense to me
That should be loading d[5][0] into element 0 and d[0][4] into element 1, but it starts 56 bytes before d. Unless I'm misreading. |
This definitely looks suspicious
|
-56 in i8 is also 200. That's the correct offset. We failed to zero extend it when we converted it from i8 to i64. So we got i64 -56 instead of i64 200. The stride is also wrong. It shoud be 16-200, -184 instead of 72. This all stems from using isSimpleVIDSequence to convert a build_vector index into a stride. We need to zero extend all the indices to XLen before we can use that I think. |
…e. NFC This shows the issue in #82430, but triggers it via the widening SEW combine rather than a GEP that RISCVGatherScatterLowering doesn't detect.
…g indices This fixes the miscompile reported in llvm#82430 by telling isSimpleVIDSequence to sign extending to XLen instead of the type of the indices, since the "sequence" of indices generated by a strided load will be at XLen. This was the simplest way I could think of of getting isSimpleVIDSequence to treat the indexes as if they were zero extended to XLenVT. Another way we could do this is by refactoring out the "get constant integers" part from isSimpleVIDSequence and handle them as APInts so we can separately zero extend it.
…g indices This fixes the miscompile reported in llvm#82430 by telling isSimpleVIDSequence to sign extending to XLen instead of the type of the indices, since the "sequence" of indices generated by a strided load will be at XLen. This was the simplest way I could think of of getting isSimpleVIDSequence to treat the indexes as if they were zero extended to XLenVT. Another way we could do this is by refactoring out the "get constant integers" part from isSimpleVIDSequence and handle them as APInts so we can separately zero extend it.
…g indices (#82506) This fixes the miscompile reported in #82430 by telling isSimpleVIDSequence to sign extend to XLen instead of the width of the indices, since the "sequence" of indices generated by a strided load will be at XLen. This was the simplest way I could think of getting isSimpleVIDSequence to treat the indexes as if they were zero extended to XLenVT. Another way we could do this is by refactoring out the "get constant integers" part from isSimpleVIDSequence and handle them as APInts so we can separately zero extend it. Fixes #82430
…e. NFC This shows the issue in llvm#82430, but triggers it via the widening SEW combine rather than a GEP that RISCVGatherScatterLowering doesn't detect. (cherry picked from commit 2cd59bd)
…g indices (llvm#82506) This fixes the miscompile reported in llvm#82430 by telling isSimpleVIDSequence to sign extend to XLen instead of the width of the indices, since the "sequence" of indices generated by a strided load will be at XLen. This was the simplest way I could think of getting isSimpleVIDSequence to treat the indexes as if they were zero extended to XLenVT. Another way we could do this is by refactoring out the "get constant integers" part from isSimpleVIDSequence and handle them as APInts so we can separately zero extend it. Fixes llvm#82430 (cherry picked from commit 815644b)
/pull-request #82572 |
…e. NFC This shows the issue in llvm#82430, but triggers it via the widening SEW combine rather than a GEP that RISCVGatherScatterLowering doesn't detect. (cherry picked from commit 2cd59bd)
…g indices (llvm#82506) This fixes the miscompile reported in llvm#82430 by telling isSimpleVIDSequence to sign extend to XLen instead of the width of the indices, since the "sequence" of indices generated by a strided load will be at XLen. This was the simplest way I could think of getting isSimpleVIDSequence to treat the indexes as if they were zero extended to XLenVT. Another way we could do this is by refactoring out the "get constant integers" part from isSimpleVIDSequence and handle them as APInts so we can separately zero extend it. Fixes llvm#82430 (cherry picked from commit 815644b)
Testcase:
Commands:
Bugpoint, ASM, red.c: c-asm-bc.zip
--opt-bisect-limit
points toSLPVectorizerPass
Discovered/tested using 7f3980a (not bisected)
Found using fuzzer
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