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Closed
12 tasks
Tracked by #99235 ...
farzonl opened this issue Jul 16, 2024 · 1 comment · Fixed by #113623
Closed
12 tasks
Tracked by #99235 ...

Implement the dot4add_i8packed HLSL Function #99220

farzonl opened this issue Jul 16, 2024 · 1 comment · Fixed by #113623
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backend:DirectX backend:SPIR-V bot:HLSL clang:codegen IR generation bugs: mangling, exceptions, etc. HLSL HLSL Language Support metabug Issue to collect references to a group of similar or related issues.

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@farzonl
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farzonl commented Jul 16, 2024

  • Implement dot4add_i8packed clang builtin,
  • Link dot4add_i8packed clang builtin with hlsl_intrinsics.h
  • Add sema checks for dot4add_i8packed to CheckHLSLBuiltinFunctionCall in SemaChecking.cpp
  • Add codegen for dot4add_i8packed to EmitHLSLBuiltinExpr in CGBuiltin.cpp
  • Add codegen tests to clang/test/CodeGenHLSL/builtins/dot4add_i8packed.hlsl
  • Add sema tests to clang/test/SemaHLSL/BuiltIns/dot4add_i8packed-errors.hlsl
  • Create the int_dx_dot4add_i8packed intrinsic in IntrinsicsDirectX.td
  • Create the DXILOpMapping of int_dx_dot4add_i8packed to 163 in DXIL.td
  • Create the dot4add_i8packed.ll and dot4add_i8packed_errors.ll tests in llvm/test/CodeGen/DirectX/
  • Create the int_spv_dot4add_i8packed intrinsic in IntrinsicsSPIRV.td
  • In SPIRVInstructionSelector.cpp create the dot4add_i8packed lowering and map it to int_spv_dot4add_i8packed in SPIRVInstructionSelector::selectIntrinsic.
  • Create SPIR-V backend test case in llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_i8packed.ll

DirectX

DXIL Opcode DXIL OpName Shader Model Shader Stages
163 Dot4AddI8Packed 6.4 ()

SPIR-V

OpSDot:

Description:

Signed integer dot product of Vector 1 and Vector 2.

Result Type must be an integer type whose Width must be greater than
or equal to that of the components of Vector 1 and Vector 2.

Vector 1 and Vector 2 must have the same type.

Vector 1 and Vector 2 must be either 32-bit integers (enabled by the
DotProductInput4x8BitPacked capability) or vectors of
integer type (enabled by the DotProductInput4x8Bit or
DotProductInputAll capability).

When Vector 1 and Vector 2 are scalar integer types, Packed Vector
Format
must be specified to select how the integers are to be
interpreted as vectors.

All components of the input vectors are sign-extended to the bit width
of the result’s type. The sign-extended input vectors are then
multiplied component-wise and all components of the vector resulting
from the component-wise multiplication are added together. The resulting
value will equal the low-order N bits of the correct result R, where N
is the result width and R is computed with enough precision to avoid
overflow and underflow.

Capability:
DotProduct

Missing before version 1.6.

Word Count Opcode Results Operands

5 + variable

4450

<id>
Result Type

Result <id>

<id>
Vector 1

<id>
Vector 2

Optional
Packed Vector Format
Packed Vector Format

Test Case(s)

Example 1

//dxc dot4add_i8packed_test.hlsl -T lib_6_8 -enable-16bit-types -O0

export int fn(uint p1, uint p2, int p3) {
    return dot4add_i8packed(p1, p2, p3);
}

HLSL:

Syntax

int dot4add_i8packed(uint a, uint b, int c);

Type Description

Name Template Type Component Type Size
ret scalar int 1
a scalar uint 1
b scalar uint 1
c scalar int 1

Minimum Shader Model

This function is supported in the following shader models.

Shader Model Supported
Shader Model 6.4 and higher shader models yes

Shader Stages

See also

@farzonl farzonl added backend:DirectX backend:SPIR-V bot:HLSL HLSL HLSL Language Support metabug Issue to collect references to a group of similar or related issues. labels Jul 16, 2024
@damyanp damyanp moved this to Ready in HLSL Support Oct 9, 2024
@inbelic inbelic self-assigned this Oct 21, 2024
@damyanp damyanp moved this from Ready to Active in HLSL Support Oct 22, 2024
@inbelic inbelic moved this from Active to Needs Review in HLSL Support Oct 25, 2024
@inbelic inbelic moved this from Needs Review to Ready in HLSL Support Nov 5, 2024
@inbelic inbelic moved this from Ready to Closed in HLSL Support Nov 5, 2024
@inbelic inbelic closed this as completed by moving to Closed in HLSL Support Nov 5, 2024
inbelic added a commit that referenced this issue Nov 5, 2024
- create a clang built-in in Builtins.td
- link dot4add_i8packed in hlsl_intrinsics.h
- add lowering to spirv backend through expansion of operation as OPSDot
is missing up to SPIRV 1.6 in SPIRVInstructionSelector.cpp
- add lowering to spirv backend using OpSDot in applicable SPIRV version
or if SPV_KHR_integer_dot_product is enabled
- add dot4add_i8packed intrinsic to IntrinsicsDirectX.td and mapping to
DXIL.td op Dot4AddI8Packed

- add tests for HLSL intrinsic lowering to dx/spv intrinsic in
dot4add_i8packed.hlsl
- add tests for sema checks in dot4add_i8packed-errors.hlsl
- add test of spir-v lowering in SPIRV/dot4add_i8packed.ll
- add test to dxil lowering in DirectX/dot4add_i8packed.ll
    
 Resolves #99220
@EugeneZelenko EugeneZelenko added the clang:codegen IR generation bugs: mangling, exceptions, etc. label Nov 5, 2024
@llvmbot
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llvmbot commented Nov 5, 2024

@llvm/issue-subscribers-clang-codegen

Author: Farzon Lotfi (farzonl)

- [ ] Implement `dot4add_i8packed` clang builtin, - [ ] Link `dot4add_i8packed` clang builtin with `hlsl_intrinsics.h` - [ ] Add sema checks for `dot4add_i8packed` to `CheckHLSLBuiltinFunctionCall` in `SemaChecking.cpp` - [ ] Add codegen for `dot4add_i8packed` to `EmitHLSLBuiltinExpr` in `CGBuiltin.cpp` - [ ] Add codegen tests to `clang/test/CodeGenHLSL/builtins/dot4add_i8packed.hlsl` - [ ] Add sema tests to `clang/test/SemaHLSL/BuiltIns/dot4add_i8packed-errors.hlsl` - [ ] Create the `int_dx_dot4add_i8packed` intrinsic in `IntrinsicsDirectX.td` - [ ] Create the `DXILOpMapping` of `int_dx_dot4add_i8packed` to `163` in `DXIL.td` - [ ] Create the `dot4add_i8packed.ll` and `dot4add_i8packed_errors.ll` tests in `llvm/test/CodeGen/DirectX/` - [ ] Create the `int_spv_dot4add_i8packed` intrinsic in `IntrinsicsSPIRV.td` - [ ] In SPIRVInstructionSelector.cpp create the `dot4add_i8packed` lowering and map it to `int_spv_dot4add_i8packed` in `SPIRVInstructionSelector::selectIntrinsic`. - [ ] Create SPIR-V backend test case in `llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_i8packed.ll`

DirectX

DXIL Opcode DXIL OpName Shader Model Shader Stages
163 Dot4AddI8Packed 6.4 ()

SPIR-V

OpSDot:

Description:

Signed integer dot product of Vector 1 and Vector 2.

Result Type must be an integer type whose Width must be greater than
or equal to that of the components of Vector 1 and Vector 2.

Vector 1 and Vector 2 must have the same type.

Vector 1 and Vector 2 must be either 32-bit integers (enabled by the
DotProductInput4x8BitPacked capability) or vectors of
integer type (enabled by the DotProductInput4x8Bit or
DotProductInputAll capability).

When Vector 1 and Vector 2 are scalar integer types, Packed Vector
Format
must be specified to select how the integers are to be
interpreted as vectors.

All components of the input vectors are sign-extended to the bit width
of the result’s type. The sign-extended input vectors are then
multiplied component-wise and all components of the vector resulting
from the component-wise multiplication are added together. The resulting
value will equal the low-order N bits of the correct result R, where N
is the result width and R is computed with enough precision to avoid
overflow and underflow.

Capability:
DotProduct

Missing before version 1.6.

<table style="width:100%;">
<colgroup>
<col style="width: 14%" />
<col style="width: 14%" />
<col style="width: 14%" />
<col style="width: 14%" />
<col style="width: 14%" />
<col style="width: 14%" />
<col style="width: 14%" />
</colgroup>
<thead>
<tr>
<th>Word Count</th>
<th>Opcode</th>
<th>Results</th>
<th>Operands</th>
<th></th>
<th></th>
<th></th>
</tr>
</thead>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p>5 + variable</p></td>
<td class="tableblock halign-left valign-top"><p>4450</p></td>
<td
class="tableblock halign-left valign-top"><p><em>&lt;id&gt;</em><br />
<em>Result Type</em></p></td>
<td class="tableblock halign-left valign-top"><p><a
href="#ResultId"><em>Result &lt;id&gt;</em></a></p></td>
<td
class="tableblock halign-left valign-top"><p><em>&lt;id&gt;</em><br />
<em>Vector 1</em></p></td>
<td
class="tableblock halign-left valign-top"><p><em>&lt;id&gt;</em><br />
<em>Vector 2</em></p></td>
<td class="tableblock halign-left valign-top"><p>Optional<br />
<a href="#Packed_Vector_Format"><em>Packed Vector Format</em></a><br />
<em>Packed Vector Format</em></p></td>
</tr>
</tbody>
</table>

Test Case(s)

Example 1

//dxc dot4add_i8packed_test.hlsl -T lib_6_8 -enable-16bit-types -O0

export int fn(uint p1, uint p2, int p3) {
    return dot4add_i8packed(p1, p2, p3);
}

HLSL:

Syntax

int dot4add_i8packed(uint a, uint b, int c);

Type Description

Name Template Type Component Type Size
ret scalar int 1
a scalar uint 1
b scalar uint 1
c scalar int 1

Minimum Shader Model

This function is supported in the following shader models.

Shader Model Supported
Shader Model 6.4 and higher shader models yes

Shader Stages

See also

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