Skip to content

[Xtensa] Implement sextload i8 #106053

New issue

Have a question about this project? # for a free GitHub account to open an issue and contact its maintainers and the community.

#

By clicking “#”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? # to your account

Merged
merged 2 commits into from
Aug 26, 2024
Merged

[Xtensa] Implement sextload i8 #106053

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
68abaf1
[Xtensa] Implement sextload i8.
andreisfr Aug 25, 2024
625086e
[Xtensa] Fix load test
andreisfr Aug 26, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 2 additions & 1 deletion llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -70,11 +70,12 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand);

// No sign extend instructions for i1
// No sign extend instructions for i1 and sign extend load i8
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Comments should end with a period.

for (MVT VT : MVT::integer_valuetypes()) {
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

FWIW you only need to set actions for legal VTs, that is only for VT == MVT::i32.

setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
}

setOperationAction(ISD::ConstantPool, PtrVT, Custom);
Expand Down
12 changes: 12 additions & 0 deletions llvm/test/CodeGen/Xtensa/load.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=xtensa < %s | FileCheck %s

define signext i8 @test_load_i8(ptr %p){
; CHECK-LABEL: test_load_i8:
; CHECK: l8ui a8, a2, 0
; CHECK-NEXT: slli a8, a8, 24
; CHECK-NEXT: srai a2, a8, 24
; CHECK-NEXT: ret
%1 = load i8, ptr %p, align 1
ret i8 %1
}
Loading