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[AArch64] Combine separate vector and scalar tablegen SDNode record for AArch64ISD::REV16. NFC #125614

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merged 2 commits into from
Feb 4, 2025
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[AArch64] Combine separate vector and scalar tablegen SDNode record for AArch64ISD::REV16. NFC #125614

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cedcb9d
[AArch64] Combine separate vector and scalar tablegen SDNode record f…
topperc Feb 4, 2025
9136a33
fixup! Add SDTypeProfile for all REV operations.
topperc Feb 4, 2025
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14 changes: 6 additions & 8 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -428,7 +428,6 @@ def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
SDTCisVT<2, OtherVT>]>;


def SDT_AArch64CSel : SDTypeProfile<1, 4,
[SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>,
Expand All @@ -451,6 +450,7 @@ def SDT_AArch64FCCMP : SDTypeProfile<1, 5,
def SDT_AArch64FCmp : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
SDTCisFP<1>,
SDTCisSameAs<2, 1>]>;
def SDT_AArch64Rev : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>]>;
def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
def SDT_AArch64Insr : SDTypeProfile<1, 2, [SDTCisVec<0>]>;
Expand Down Expand Up @@ -817,11 +817,9 @@ def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;

def AArch64rev16_scalar : SDNode<"AArch64ISD::REV16", SDTIntUnaryOp>;

def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64Rev>;
def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64Rev>;
def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64Rev>;
def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;

def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
Expand Down Expand Up @@ -3000,8 +2998,8 @@ def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
def : Pat<(srl (bswap top16Zero:$Rn), (i64 16)), (REV16Wr GPR32:$Rn)>;
def : Pat<(srl (bswap top32Zero:$Rn), (i64 32)), (REV32Xr GPR64:$Rn)>;

def : Pat<(AArch64rev16_scalar GPR32:$Rn), (REV16Wr GPR32:$Rn)>;
def : Pat<(AArch64rev16_scalar GPR64:$Rn), (REV16Xr GPR64:$Rn)>;
def : Pat<(AArch64rev16 GPR32:$Rn), (REV16Wr GPR32:$Rn)>;
def : Pat<(AArch64rev16 GPR64:$Rn), (REV16Xr GPR64:$Rn)>;

def : Pat<(or (and (srl GPR64:$Rn, (i64 8)), (i64 0x00ff00ff00ff00ff)),
(and (shl GPR64:$Rn, (i64 8)), (i64 0xff00ff00ff00ff00))),
Expand Down