Skip to content

[X86] Fold (add X, (srl Y, 7)) -> (sub X, (ashr Y, 7)) on vXi8 vectors #143106

New issue

Have a question about this project? # for a free GitHub account to open an issue and contact its maintainers and the community.

#

By clicking “#”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? # to your account

Merged
merged 1 commit into from
Jun 6, 2025
+421 −448
Merged

[X86] Fold (add X, (srl Y, 7)) -> (sub X, (ashr Y, 7)) on vXi8 vectors #143106

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
20 changes: 15 additions & 5 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -58113,13 +58113,14 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
}
}

// If vectors of i1 are legal, turn (add (zext (vXi1 X)), Y) into
// (sub Y, (sext (vXi1 X))).
// FIXME: We have the (sub Y, (zext (vXi1 X))) -> (add (sext (vXi1 X)), Y) in
// generic DAG combine without a legal type check, but adding this there
// caused regressions.
if (VT.isVector()) {
SDValue X, Y;

// If vectors of i1 are legal, turn (add (zext (vXi1 X)), Y) into
// (sub Y, (sext (vXi1 X))).
// FIXME: We have the (sub Y, (zext (vXi1 X))) -> (add (sext (vXi1 X)), Y)
// in generic DAG combine without a legal type check, but adding this there
// caused regressions.
EVT BoolVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
VT.getVectorElementCount());
if (DAG.getTargetLoweringInfo().isTypeLegal(BoolVT) &&
Expand All @@ -58128,6 +58129,15 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, X);
return DAG.getNode(ISD::SUB, DL, VT, Y, SExt);
}

// Fold (add X, (srl Y, 7)) -> (sub X, (ashr Y, 7)) to undo instcombine
// canonicalisation as we don't have good vXi8 shifts.
if (VT.getScalarType() == MVT::i8 &&
sd_match(N, m_Add(m_Value(X), m_Srl(m_Value(Y), m_SpecificInt(7))))) {
SDValue AShr = DAG.getNode(ISD::SRA, DL, VT, Y,
DAG.getShiftAmountConstant(7, VT, DL));
return DAG.getNode(ISD::SUB, DL, VT, X, AShr);
}
}

// Peephole for 512-bit VPDPBSSD on non-VLX targets.
Expand Down
Loading
Loading