[RISCV] Add srmcfg CSR from Ssqosid extension.

[topperc]

Based on the spec here https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1

Ssqosid extension name will be added in a separate patch.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-mc

Author: Craig Topper (topperc)

Changes

Based on the spec here https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1

Ssqosid extension name will be added in a separate patch.

---

Full diff: https://github.com/llvm/llvm-project/pull/79914.diff

2 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVSystemOperands.td (+5)
• (modified) llvm/test/MC/RISCV/supervisor-csr-names.s (+18)

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 43475e825b46fb..f046312b1d4284 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -132,6 +132,11 @@ def : SysReg<"sip", 0x144>;
 let DeprecatedName = "sptbr" in
 def : SysReg<"satp", 0x180>;
 
+//===----------------------------------------------------------------------===//
+// Quality-of-Service(QoS) Identifiers (Ssqosid)
+//===----------------------------------------------------------------------===//
+def : SysReg<"srmcfg", 0x181>;
+
 //===----------------------------------------------------------------------===//
 // Debug/Trace Registers
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s
index 84f9edd595d093..127812de4bdc9b 100644
--- a/llvm/test/MC/RISCV/supervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/supervisor-csr-names.s
@@ -196,6 +196,24 @@ csrrs t1, satp, zero
 # uimm12
 csrrs t2, 0x180, zero
 
+#########################################
+# Quality-of-Service(QoS) Identifiers
+#########################################
+
+# srmcfg
+# name
+# CHECK-INST: csrrs t1, srmcfg, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x18]
+# CHECK-INST-ALIAS: csrr t1, srmcfg
+# uimm12
+# CHECK-INST: csrrs t2, srmcfg, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x18]
+# CHECK-INST-ALIAS: csrr t2, srmcfg
+# name
+csrrs t1, srmcfg, zero
+# uimm12
+csrrs t2, 0x181, zero
+
 #########################################
 # Debug/Trace Registers
 #########################################

[preames]

Two questions.

1. Where in the specification is the register number mentioned? I didn't find it with some quick searching.

2. Do we need to do anything special to worry about sysregs of different sizes? This one is SXLEN-bit for instance, and I don't see that obviously being reflected here.

[topperc]

1. End of the paragraph at the beginning of Chapter 2.

The srmcfg register is an SXLEN-bit read/write register used to configure a Resource Control ID (RCID) and a Monitoring Counter ID (MCID). Both RCID and MCID are WARL fields. The register is
formatted as shown in Figure 1 when SXLEN=64 and Figure 2 when SXLEN=32. The CSR number is
0x181.

2. I don't think so. The only thing I know about is registers that have a high register for RV32.

[preames]

On the register number, I swear I grepped for those words. Thanks.

[preames]

LGTM