v0.5.0

New Features

• Rework on Signal Bundles in #25
• Standard Bundles in #26
• Verilog Wrapper Generator in #28

Bug Fix

• Fix: Multiply width Inference in #24

Project related

• Defining project structure in #30

Full Changelog: v0.4.1...v0.5.0

v0.4.1

What's Changed

• Fix: Comment in Annotation is optional in #22 and #23

Full Changelog: v0.4.0...v0.4.1

v0.4.0

New Features

• One Hot En/Decoding in #10
• Module Spec Generation and Auto Doc in Verilog Code in #14
• Annotate signal in Elaborated SV Code with Signal.annotate() in #21
  • Thank you @yaus for suggesting this feature in #11
• Refined Integrating by Mounting Verilator into the virtualenv in #20
  • It's now used by tests only, but will consider pulling it out for workflow integration.

Breaking changes

• Rename the Project in #16
• Python package now named magia-hdl. Installation script: pip install magia-hdl

Acknowledgement

• Thanks @yaus for raising and fixing a broken test case for python <=3.9 by in #17 and #18
• Thanks @tklam for raising and assisting on the Verilator Integration failure in Virtual Env in #19 and #20

Full Changelog: v0.3.0...v0.4.0

v0.3.0

New Features

• Import external module in #9
  • Thanks @yaus for proposing this feature
• Fixed-point conversion class. Magia.std.fixed_point
• Signal.parity() for Reduce XOR operation
  • Thanks @yaus for implementing with testing on other operators this in #3
• binary_to_onehot convertor in magia.std.encoding

Breaking changes

• Module.elaborate_all() is deprecated.
  • Use the Elaborator helper class instead.
• Renamed SDP, DP, TDP shorthands function for Memory for formatting.

Documentation

• Project Roadmap in #6
• Contribution Guideline in #8

Full Changelog: v0.2.0...v0.3.0

v0.2.0

New Features

• Memory Syntax
• Elaborator: Simplified elaboration methods.
  • Thanks @yaus for the suggestion on Issue #2
• New API on Signal: signal.with_width() and signal.with_signed()
  • They create signals with new width/signedness, connected to the source signal.

Minor Changes

• Operands of +,-,* operators must have the same signedness
• <<, >> Arithmetic/Logical Shift is selected depending on signal signedness.
• Adding Tests

v0.1.0

Initial Release

• Syntax defined in doc/syntax.md is implemented
• Capability to elaborate modules into SystemVerilog by Module.elaborate(modules)
• Basic Documentation