ARM-verilog

designing an arm processor, using verilog

Name		Name	Last commit message	Last commit date
Latest commit History 35 Commits
CPU-Pipeline.v		CPU-Pipeline.v
CPU-SingleCycle-Readable.v		CPU-SingleCycle-Readable.v
CPU-SingleCycle.v		CPU-SingleCycle.v
README.md		README.md
adder.v		adder.v
alu.v		alu.v
alu_control.v		alu_control.v
clock.v		clock.v
control_unit.v		control_unit.v
instruction_memory.v		instruction_memory.v
instruction_memory_pipeline.v		instruction_memory_pipeline.v
memory.v		memory.v
mux2.v		mux2.v
register.v		register.v
register_bank.v		register_bank.v
shift_left.v		shift_left.v
sign_extend.v		sign_extend.v

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