Instruction set simulator for RISC-V
Swimmer-RISCV is configurable instruction set simulator written in C++.
riscv-isa-sim(Spike) is very fast and simple RISC-V simulator written in C++.
Swimmer-RISCV is designed for debugging RISC-V program, using --trace-hier
option can generate function call tree.
--debug
option can generate all information such as register read/write and memory access.
Swimmer-RISCV is tested on Ubuntu 18.04 LTS and CentOS 7.2 with GCC 8.1.0 For Ubuntu, following packages are need to be install:
sudo apt install -y libbfd-dev device-tree-compiler python3-dev libpython3-dev pkg-config
riscv-tests repository is used to run regression test using Swimmer-RISCV. It is recommended to install riscv-tools and $RISCV environment variable should be set.
usage: ./swimmer_riscv [options] ...
options:
--max_size Max size of log file [MB] (unsigned int [=0])
--max Max instructions to simulate (unsigned long [=0])
--binfile Binary file to simulate. (string [=])
--hexfile Hex file to simulate. (string [=])
--only_info_load Debug Info is only loaded (only enable with --binfile)
--debug Generate debug log
--out Output log filename (string [=])
--load-dump Dump Loaded Bin file (only enable with --binfile)
--parallel CPU Parallel Execution
--init_pc Initial Program Counter Value (string [=])
--stop-host Stop simulation by accessing MTOHOST
--use-pk Location of RISC-V Proxy Kernel (string [=])
--arch Support RISC-V Architecture (ex. --arch rv32imafd.../rv64imafd...) (string [=rv64imafdc])
--trace-hier Generate Hierarcical Trace
--trace-out Hierarcical Trace Output Filename (string [=])
--vmlinux Location of vmlinux (string [=])
--logstart cycle of log start (unsigned long [=0])
--printstep print number of steps each cycle (unsigned long [=0])
--signature Generate Signature and filename (string [=])
-v, --version Show Version Information
-?, --help print this message
--max_size
: Max size of simulation log file generated with--out
option.--max
: Max number of instruction to be simulated.--binfile
: RISC-V binary file to be simulated.--hexfile
: RISC-V srec file to be simulated.--only_info_load
: only load RISC-V binary BFD information. Simulation doesn't start.--debug
: Generate debug information.--out
: Filename of debug information.--load-dump
: Show load binary dump--init_pc
: Specify intial program counter address. If not specify, Swimmer autamatically sets PC by reading RISC-V binary.--stop-host
: Simulator stops when accessing tohost/fromhost memory address.--use-pk
: Specify location of Proxy Kernel.--bit-mode
: Bit mode. 32 or 64.--trace-hier
: Generate Function call hierarchy.--trace-out
: Filename of Functional call hierarchy.--vmlinux
: Specify location of vmlinux object. It is for simulate RISC-V Linux.--logstart
: Number of instructions that starts to generate simulation log.--printstep
: Swimmer generates Step information for each step.--signature
: Swimmer generates signature for riscv-torture.
$ cat test.c
#include <stdio.h>
main () { printf("Hello\n"); }
$ riscv64-unknown-elf-gcc test.c -o test.elf
$ swimmer_riscv --binfile test.elf --use-pk ${RISCV}/riscv64-unknown-elf/bin/pk
Hello
Now Swimmer-RISCV supports Linux binary generated by Freedom-U-SDK.
$ swimmer_riscv --binfile freedom-u-sdk/work/riscv-pk/bbl
For Release Build:
cd build
cmake . -DCMAKE_BUILD_TYPE=Release
make
10 / 402 patterns in riscv-tests are failed now.
Pattern Name | Status |
---|---|
rv32mi-p-mcsr | Fail |
rv32uc-v-rvc | Fail |
rv32mi-p-illegal | Fail |
rv32mi-p-breakpoint | Fail |
rv32mi-p-ma_fetch | Fail |
rv64uc-v-rvc | Fail |
rv64mi-p-breakpoint | Fail |
rv64mi-p-access | Fail |
rv64mi-p-illegal | Fail |
rv64mi-p-ma_fetch | Fail |
Email : msyksphinz.dev@gmail.com