Computer-Architecture

This is the laboratory assignment for the course Computer Architecture.

The final result of this project is a pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and the cache.

My collaborator is Yuheng ZHOU.

Name		Name	Last commit message	Last commit date
Latest commit History 67 Commits
Topic 1. Multiple-cycle CPU Design		Topic 1. Multiple-cycle CPU Design
Topic 2. Pipelined CPU with stall		Topic 2. Pipelined CPU with stall
Topic 3. Pipelined CPU with forwarding		Topic 3. Pipelined CPU with forwarding
Topic 4. Pipelined CPU resolving control hazard		Topic 4. Pipelined CPU resolving control hazard
Topic 5. Pipelined CPU support 31 MIPS Instructions.pdf		Topic 5. Pipelined CPU support 31 MIPS Instructions.pdf
Topic 6. Pipelined CPU supporting interrupt		Topic 6. Pipelined CPU supporting interrupt
Topic 7. Cache Line Design		Topic 7. Cache Line Design
Topic 8. Pipelined CPU with Cache		Topic 8. Pipelined CPU with Cache
README.md		README.md

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