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cv32e40s ldgen bugfix #1991
cv32e40s ldgen bugfix #1991
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silabs-hfegran
commented
Jun 20, 2023
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- Fixed: Random tablejump sequence used hardcoded T0 register (Caused stack corruption)
- Fixed: linker script generator run standalone does not get the correct include-files and errs on uvm macro that does not exist
- Fixed: ldgen: Added support for configurations where not the entire memory map is writable
- Fixed: -nmagic flag added (prevents linker from embedding the elf header into the first program header segment) This caused a binary mismatch between the output of objcopy and the contents of the program headers in the elf. The ISS only parses the program headers to decide what ends up in memory (correct from a program loader point of view but does not make sense for an embedded bare metal target). Objcopy that creates the raw binary for the RTL only parses the section header, which does not include this part of the binary, and thus there is a mismatch when this region is read without first being written by the program.
- Fixed: Non-sensical debug region settings
- Fixed: Missing enablement of "random instruction for hint"-setting in cpuctrl
- Summary: Improved full regression test results from ~25/824 failures to ~4/824 failures
Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>
Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>
I'll need some hand-holding to fully understand much of this. |
When this PR Is fully ready I will give you a rundown of the changes - just want to double check a couple of items here before this is done. |
Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>
Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>
Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>
While the GNU documentation for the -nmagic flag is rather sparse, I came across this comment on a LLVM PR that shed some light on the issue (different compiler, but gnu ld appears to behave this way as well), the undocumented behavior is the key here:
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Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>
Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>
…tting to riscv-dv Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>
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Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>
Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>
Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>
Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>
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Approving based on:
Much of this has been discussed IRL.
The rest of it will be put on trial via regressions.
I have skimmed through everything and see nothing that should be objected to.