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Both rd and rs1 get value of rd_rs1 in build_asm #2068

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merged 5 commits into from
Jul 21, 2023
Merged

Both rd and rs1 get value of rd_rs1 in build_asm #2068

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a0b899a
Both rd and rs1 get value of rd_rs1 in build_asm
silabs-inhaahje Jul 20, 2023
67f921d
Removed return statement causing wrong hint instruction disassembly
silabs-hfegran Jul 20, 2023
9b6bcdc
Changed nonblocking assignment to blocking in always_comb block
silabs-hfegran Jul 20, 2023
4bded47
rs1 not valid for c.li instruction
silabs-inhaahje Jul 21, 2023
90d91c3
Merge branch 'disassembler_updates' of github.com:silabs-inhaahje/cor…
silabs-inhaahje Jul 21, 2023
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4 changes: 4 additions & 0 deletions lib/support/isa_support.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1407,9 +1407,11 @@
asm.imm.valid = 0;
end else if (name inside { C_MV }) begin
asm.rd.gpr = instr.compressed.format.cr.rd_rs1.gpr;
asm.rs1.gpr = instr.compressed.format.cr.rd_rs1.gpr;
asm.rs2.gpr = instr.compressed.format.cr.rs2.gpr;
asm.rd.valid = 1;
asm.rs2.valid = 1;
asm.rs1.valid = 1;
end else if (name inside { C_ADD }) begin
asm.rd.gpr = instr.compressed.format.cr.rd_rs1.gpr;
asm.rs1.gpr = instr.compressed.format.cr.rd_rs1.gpr;
Expand All @@ -1427,13 +1429,15 @@
CI_TYPE: begin
if (name inside { C_LI, C_NOP, C_ADDI }) begin
asm.rd.gpr = instr.compressed.format.ci.rd_rs1.gpr;
asm.rs1.gpr = instr.compressed.format.ci.rd_rs1.gpr;
asm.imm.imm_raw = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 };
asm.imm.imm_raw_sorted = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 };
asm.imm.imm_type = IMM;
asm.imm.width = 6;
asm.imm.sign_ext = 1;
asm.imm.imm_value = get_imm_value_ci({ instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 });
asm.rd.valid = 1;
asm.rs1.valid = 1;
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asm.imm.valid = 1;
end else if (name == C_LUI) begin
asm.rd.gpr = instr.compressed.format.ci.rd_rs1.gpr;
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