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Ccover s #2216
Ccover s #2216
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Signed-off-by: Kristine Dosvik <krdosvik@silabs.com>
…essary signal from assert Signed-off-by: Kristine Dosvik <krdosvik@silabs.com>
@@ -1,164 +1,197 @@ | |||
<?xml version="1.0" encoding="UTF-8" standalone="no"?> | |||
<refinement-file-root> | |||
<information comment-version="1" creation-time="Fri 08 Sep 2023 16:33:54 CEST" creator="krdosvik" csCheck="true" modified-by="krdosvik" modify-time="Fri 22 Sep 2023 15:00:52 CEST" save-ref-method="seq" tool-version="Cadence vManager22.05" rules-signature-c="5ec06b80ed3aa56a354242dc7124e080"> |
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Hem, that I have changed this file was a bit unexpected. I will let it be a drafth PR to I have figured it out.
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manual_expression_cov_todo.vRefine seems to have changes that was also stored and modified (for the better) in the xsecure_trigger file.
.../tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert.sv
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Signed-off-by: Kristine Dosvik <krdosvik@silabs.com>
…r_express_cov file Signed-off-by: Kristine Dosvik <krdosvik@silabs.com>
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Approving based on:
Expression coverage analysis is a nice addition.
Test status reported to be ok.
"Removed signal from assertions as it was not unnecessary" broadens the antecedent, so that should be a safe move.
Added vRefine file for some xsecure and trigger.
Removed signal from assertions as it was not unnecessary (assert property(!resp_ph_cont) passes).
Unglitched formal compiles,
Glitched formal passes.
The assertions are disabled in normal ci check, so have not tested it, but at least hello-world passes.