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Cv32e40s/dev -> master #2257

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eea7704
Fixed errors+cleanup in uvma_pma_sb
silabs-hfegran Jun 29, 2023
2c8410e
Fixed missing return statement
silabs-hfegran Jun 29, 2023
1556968
Merge pull request #2010 from silabs-krdosvik/remove_CLIC_INTTHRESHBITS
silabs-hfegran Jun 29, 2023
34976af
Fixed debug_priv_test issue with word load/store for byte variable
silabs-hfegran Jun 30, 2023
80a6d57
fixed struct mtvt_t to work with small id widths
silabs-mateilga Jul 4, 2023
c04d577
Merge pull request #2024 from silabs-mateilga/clic_assert_mtvt_fields
silabs-hfegran Jul 4, 2023
64209a9
Merge pull request #1991 from silabs-hfegran/dev_hf_ldgen_bugfix
silabs-robin Jul 4, 2023
2764c92
Updated regression scripts to fix issues with --iss 0
silabs-hfegran Jul 5, 2023
4c23abf
Merge pull request #2025 from silabs-robin/xdev_revitalized
silabs-hfegran Jul 5, 2023
3b12420
Merge pull request #2026 from silabs-hfegran/dev_hf_regression_script…
silabs-robin Jul 5, 2023
bbcffd6
Removed b_ext_abs cfg from b-ext test in full regression (incompatibl…
silabs-hfegran Jul 5, 2023
1766deb
Merge pull request #2027 from silabs-hfegran/dev_hf_remove_b_abs_cfg
silabs-robin Jul 5, 2023
7e3d444
use hash=709bec4 instead of main in clonetb
silabs-krdosvik Jul 6, 2023
4e8836a
Merge pull request #2030 from silabs-krdosvik/new_b
silabs-robin Jul 6, 2023
d1f528d
Merge branch 'cv32e40s/dev' of github.com:openhwgroup/core-v-verif in…
silabs-krdosvik Jul 6, 2023
b91d76f
unfinished clic asserts disabled, wip
silabs-mateilga Jul 7, 2023
ed18a97
update to correct hash in bin/clonetb
silabs-krdosvik Jul 7, 2023
40f77e7
Merge pull request #2031 from silabs-krdosvik/xdev_merge_in_sdev
silabs-robin Jul 10, 2023
926329f
cv32e40x contains only a readme
silabs-krdosvik Jul 10, 2023
f207535
Added Zc* instructions to disassembler
silabs-inhaahje Jul 10, 2023
e8e1a85
Merge pull request #2036 from silabs-krdosvik/delete-cv32e40x
silabs-robin Jul 10, 2023
6606805
Merge pull request #2038 from silabs-krdosvik/merge-x-into-s
silabs-robin Jul 10, 2023
8f3f3a5
Updates on hint functions and removed forgotten comments
silabs-inhaahje Jul 10, 2023
3cfa633
updated get_stack_adj function to use case statement with inside
silabs-inhaahje Jul 11, 2023
5d14856
Made enums of funct3 and funct5
silabs-inhaahje Jul 11, 2023
40a9b9b
removed signals set to default value in build_asm function
silabs-inhaahje Jul 11, 2023
7b800ad
Removed signals set to default value(0) also on first if statement of…
silabs-inhaahje Jul 11, 2023
4db547f
Merge pull request #2037 from silabs-inhaahje/disassembler_updates
silabs-hfegran Jul 11, 2023
121c195
Added clic tests to cover coverage holes, fixed clic test issues
silabs-hfegran Jul 12, 2023
a35cf07
Removed superfluous typecast of constant
silabs-hfegran Jul 12, 2023
1dbc740
Fixed wrong type usage
silabs-hfegran Jul 13, 2023
5ad2761
Merge pull request #2035 from silabs-mateilga/clic_asserts_temp_fix
silabs-hfegran Jul 13, 2023
71bb3be
fixed incorrect funct3 for c.andi, c.addi and c.nop
silabs-inhaahje Jul 13, 2023
84d4f18
Merge pull request #2050 from silabs-inhaahje/disassembler_updates
silabs-hfegran Jul 13, 2023
042fbc5
Merge pull request #2046 from silabs-hfegran/dev_hf_clic_test_updates
silabs-hfegran Jul 13, 2023
a926f53
Added support for 40X in debug_test2, fixed typo
silabs-hfegran Jul 13, 2023
1e44cae
Merge pull request #2051 from silabs-hfegran/dev_hf_dbg2_40x_support
silabs-robin Jul 13, 2023
4a0d0c9
Changed outputs from logic to bit and fixed case statement in decode_…
silabs-inhaahje Jul 14, 2023
2b57220
Fixed alignment
silabs-inhaahje Jul 14, 2023
bf85182
Fixed more alignments
silabs-inhaahje Jul 14, 2023
3a167ef
Merge pull request #2055 from silabs-inhaahje/disassembler_updates
silabs-hfegran Jul 14, 2023
526c9fa
Added assertion to verify trap for unknown_instr
silabs-inhaahje Jul 14, 2023
7e3c7b2
Fixed error message to trapped
silabs-inhaahje Jul 14, 2023
0ee49d0
Merge pull request #2056 from silabs-inhaahje/disassembler_assertions
silabs-robin Jul 14, 2023
1c3e8bb
Made it possible to use the Risc-v disassembler with isacov
silabs-inhaahje Jul 18, 2023
fbffaed
Corrected alignment
silabs-inhaahje Jul 18, 2023
0dcced7
Refactored testbench code, moved iss initialization to uvm_reset_phas…
silabs-hfegran Jul 18, 2023
7de59a3
Changed to isa_support and shortened if statement
silabs-inhaahje Jul 18, 2023
c579d8a
Split up the if statement in order to reduce repeated code
silabs-inhaahje Jul 18, 2023
e041fb9
Made Spike the default decoder
silabs-inhaahje Jul 19, 2023
5b10a1a
Merge pull request #2059 from silabs-inhaahje/isacov_disassembler
silabs-robin Jul 19, 2023
3f84f69
Fixed tab/space-issues
silabs-hfegran Jul 20, 2023
f9c3848
Merge pull request #2060 from silabs-hfegran/dev_hf_tb_refactor
silabs-hfegran Jul 20, 2023
c565495
Fixed c_addi instruction in isa_support
silabs-inhaahje Jul 20, 2023
80513b4
Fixed alignment
silabs-inhaahje Jul 20, 2023
d28dd1d
Merge pull request #2067 from silabs-inhaahje/disassembler_updates
silabs-hfegran Jul 20, 2023
a0b899a
Both rd and rs1 get value of rd_rs1 in build_asm
silabs-inhaahje Jul 20, 2023
67f921d
Removed return statement causing wrong hint instruction disassembly
silabs-hfegran Jul 20, 2023
9b6bcdc
Changed nonblocking assignment to blocking in always_comb block
silabs-hfegran Jul 20, 2023
4bded47
rs1 not valid for c.li instruction
silabs-inhaahje Jul 21, 2023
90d91c3
Merge branch 'disassembler_updates' of github.com:silabs-inhaahje/cor…
silabs-inhaahje Jul 21, 2023
a32459e
Merge pull request #2068 from silabs-inhaahje/disassembler_updates
silabs-hfegran Jul 21, 2023
89a2371
Expanded disassembler with A extension. Not tested
silabs-inhaahje Jul 21, 2023
7c4b526
Added illegal access tests for mscratchcsw* to clic test
silabs-hfegran Jul 24, 2023
6a8c5d0
Merge pull request #2074 from silabs-hfegran/dev_hf_mscratchcsw_illeg…
silabs-robin Jul 24, 2023
12a4f0f
Split up funct5 and updated funct3_a with W and D
silabs-inhaahje Jul 26, 2023
e002195
Fixed issue with always_comb block using signals written within
silabs-hfegran Jul 27, 2023
c716e5e
Merge pull request #2086 from silabs-hfegran/dev_hf_always_comb_issue…
silabs-robin Jul 27, 2023
2924306
Temporary fix to get ISS regression runs going
silabs-hfegran Jul 27, 2023
9ee971f
Merge pull request #2087 from silabs-hfegran/dev_hf_volatile_clic_tem…
silabs-robin Jul 27, 2023
624ba38
Merge pull request #2070 from silabs-inhaahje/disassembler_updates
silabs-hfegran Jul 27, 2023
7e80632
Fixed issue where clic tests would fail due to (unintended) too high …
silabs-hfegran Jul 27, 2023
15be17e
Merge pull request #2089 from silabs-hfegran/dev_hf_mintstatus_clic_t…
silabs-robin Jul 27, 2023
c9dde44
Added wfe wakeup uvm agent
silabs-hfegran Aug 1, 2023
7d4de46
Removed unnecessary and confusing is_active signal
silabs-hfegran Aug 2, 2023
fc4319f
Updated/fixed interrupt asserts (wfe, w,memhog-related)
silabs-hfegran Aug 4, 2023
996b7ba
Added wfe signal to imperas_dv_wrap
silabs-hfegran Aug 4, 2023
b70f196
Added simple wfe test
silabs-hfegran Aug 4, 2023
b61166b
moved cover to avoid potential warning
silabs-hfegran Aug 7, 2023
72e162a
Merge pull request #2097 from silabs-hfegran/dev_hf_wfe_wu_agent
silabs-robin Aug 7, 2023
83f8464
Add script for merging between cv32e40x and cv32e40s development
silabs-krdosvik Aug 8, 2023
73478e8
convert comments to echos, convert _script to .sh, add licence
silabs-krdosvik Aug 8, 2023
8952000
Delete merge_script
silabs-krdosvik Aug 9, 2023
118a55d
Merge pull request #2115 from silabs-krdosvik/local_s
silabs-robin Aug 9, 2023
4a275ce
add atomic to rvfi_instr_if, expand/divide the support pkg
silabs-krdosvik Jul 27, 2023
f72731c
divided the isa_support content into the different files, fixed asser…
silabs-krdosvik Aug 9, 2023
cf0a4ee
remove commented, unpopulated dummy functions
silabs-krdosvik Aug 10, 2023
4a37a52
make isa_decoder_pkg
silabs-krdosvik Aug 13, 2023
7e34608
remove dut_wrap's core params
silabs-robin Aug 14, 2023
4c9627c
move assigns from dut_wrap to tb
silabs-robin Aug 14, 2023
1f15f26
remove unnecessary imports
silabs-robin Aug 14, 2023
330d236
make merge script 'remote name agnostic'
silabs-robin Aug 14, 2023
fdd9e5b
only use includes in pkg, change compile order in flist, extract isa …
silabs-krdosvik Aug 14, 2023
e7aa42f
Merge pull request #2116 from silabs-krdosvik/assert_fixups5
silabs-robin Aug 14, 2023
4b531ae
Merge pull request #2121 from silabs-robin/merge_script_tweak
MikeOpenHWGroup Aug 14, 2023
99541f2
Merge pull request #2120 from silabs-robin/dut_wrap_purge
silabs-robin Aug 15, 2023
dd2e053
fv: repair flist
silabs-robin Aug 15, 2023
ec22348
fv: fix some warnings
silabs-robin Aug 15, 2023
1db977c
name constants for bit indexing
silabs-robin Aug 16, 2023
e7ac38f
Merge pull request #2125 from silabs-robin/fvfix2023aug
silabs-robin Aug 16, 2023
fc55e91
Updated cv32e40s core hash to 41cbecf7690efd0ccd75b32bc31aab09c5dede56
silabs-hfegran Aug 17, 2023
a99aa9c
Merge pull request #2129 from silabs-hfegran/dev_hf_bitselect_hotfix
silabs-robin Aug 17, 2023
73cfcd0
fv: use 'ExternalRepos.mk'
silabs-robin Aug 17, 2023
15ed01d
add glitch prefix to integrity assert, better usage of decode logic i…
silabs-krdosvik Aug 17, 2023
b353c42
Merge pull request #2131 from silabs-robin/fvhash
silabs-robin Aug 17, 2023
bb62d20
add decoder signals in support logic, rename integrity enable parameter
silabs-krdosvik Aug 17, 2023
8454d09
Merge pull request #2132 from silabs-krdosvik/trigger_glitch_and_xsec…
silabs-robin Aug 17, 2023
694eea1
Added covers for nmi in debug followed by single stepping with stepie…
silabs-hfegran Aug 18, 2023
961c7cb
Simplified sequences
silabs-hfegran Aug 18, 2023
66c25d3
Fixed typo
silabs-hfegran Aug 18, 2023
2ea8901
Adressed review feedback
silabs-hfegran Aug 21, 2023
4a29c96
Rewrites and break up of two incomplete asserts
silabs-mateilga Aug 21, 2023
02c56d7
Merge pull request #2136 from silabs-hfegran/dev_hf_dbg_nmi_step_step…
silabs-robin Aug 21, 2023
3d0ff75
Updates to PR feedback
silabs-mateilga Aug 21, 2023
c3b0cba
Merge pull request #2138 from silabs-mateilga/clic_assert_updates
silabs-hfegran Aug 21, 2023
4f47aad
Rearranged signal declarations to the top of the file to fix sim
silabs-mateilga Aug 22, 2023
9e81739
Merge pull request #2142 from silabs-mateilga/signal_list_cleanup
silabs-hfegran Aug 22, 2023
0d8e7d4
cov: regenerate 'auto' vrefine
silabs-robin Aug 24, 2023
19ca713
cov: update readme, rename 'hierarchy' vrefine
silabs-robin Aug 24, 2023
8e759dc
Fixed timing for zc_test and placed printouts behind a debug define
silabs-mateilga Aug 24, 2023
3bd3267
cov: add non-dut refines
silabs-robin Aug 24, 2023
a4a8f0c
Merge pull request #2149 from silabs-mateilga/zc_test_fix
silabs-hfegran Aug 25, 2023
3e7df23
Fixed merge script not working in the morning (single-digit hours)
silabs-hfegran Aug 28, 2023
2d953a4
Merge pull request #2152 from silabs-hfegran/dev_hf_fix_merge_script_…
silabs-robin Aug 28, 2023
5580cef
cov: refine some gen-blocks
silabs-robin Aug 28, 2023
b6bd488
revise debug vplan
silabs-robin Aug 29, 2023
724b6c4
start a csv->json converter
silabs-robin Aug 30, 2023
79d26d8
clean permissions and file extension of 'xlsx2csv'
silabs-robin Aug 30, 2023
d10969e
continue 'csv2json' script
silabs-robin Aug 30, 2023
01f62db
fixed a CEX in assert a_mepc_set_correct_after_irq
silabs-mateilga Aug 31, 2023
0386b7d
Merge pull request #2165 from silabs-mateilga/clic_assert_mepc_set_fix
silabs-hfegran Aug 31, 2023
6216b5b
Resolved clic assert fixmes for mscratchcsw and mscratchcswl
silabs-hfegran Aug 31, 2023
e9ef090
Merge pull request #2166 from silabs-hfegran/dev_hf_clic_fixme
silabs-robin Aug 31, 2023
47a47d3
fix for propagating reset signal - requires IDV : commit 89b5aa66cccd…
eroom1966 Aug 31, 2023
a787bc5
Merge pull request #2169 from eroom1966/cv32e40s/dev
silabs-hfegran Sep 1, 2023
9b6c828
added asserts verifying m_none
silabs-mateilga Sep 4, 2023
005be14
Fix support logic fifo and add obi req instances
silabs-krdosvik Sep 4, 2023
802cc46
added REM
silabs-mateilga Sep 4, 2023
c82b94e
Merge pull request #2176 from silabs-mateilga/m_none_asserts
silabs-robin Sep 4, 2023
77be13b
update link to coverage, remove note in trigger asserts
silabs-krdosvik Sep 4, 2023
b3d6c58
Merge pull request #8 from silabs-krdosvik/robin_debug_vplan
silabs-robin Sep 4, 2023
7b125ff
check max outstanding obi
silabs-robin Sep 5, 2023
c7892b1
Merge pull request #2180 from silabs-robin/max_outstanding
silabs-robin Sep 5, 2023
6c5df46
A more modular FIFO, and add obi packets
silabs-krdosvik Sep 6, 2023
a61480f
Merge pull request #2164 from silabs-robin/json_vplans
MikeOpenHWGroup Sep 6, 2023
ee29ba2
Update assertions for clic spec changes, add dpc assertions
silabs-hfegran Sep 8, 2023
6fd3a0a
Merge pull request #2150 from silabs-robin/scover
silabs-hfegran Sep 8, 2023
28654c4
Cleanup, change mtvt_table_value usage for simulation
silabs-hfegran Sep 8, 2023
9451474
csv2json: only repeat certain empty cells
silabs-robin Sep 11, 2023
0c89e67
csv2json: apply to 40s vplans
silabs-robin Sep 11, 2023
9c7fbc4
use correct csr privlevel path
silabs-krdosvik Sep 13, 2023
5d8a77c
update core hash
silabs-krdosvik Sep 13, 2023
3d660f2
Merge pull request #2196 from silabs-krdosvik/xsecure
silabs-hfegran Sep 13, 2023
c666f3e
Extended the Code coverage vRefine file with some untouched xsecure code
silabs-krdosvik Sep 13, 2023
4b3fd3e
relocate vRefine file to correct location
silabs-krdosvik Sep 14, 2023
4a8a8e9
Merge pull request #2197 from silabs-krdosvik/ccover_s
silabs-robin Sep 14, 2023
68a5170
Cleanup clic assertions, add dpc_check for exception
silabs-hfegran Sep 14, 2023
aeaa67e
Merge branch 'cv32e40s/dev' into dev_hf_clic_updates
silabs-hfegran Sep 14, 2023
ff5bcbe
Merge pull request #2190 from silabs-hfegran/dev_hf_clic_updates
silabs-hfegran Sep 14, 2023
3c61629
Fixed missing granularity in pmp cov, disabled wrong pma-cover
silabs-hfegran Sep 14, 2023
15d51eb
Merge pull request #2201 from silabs-hfegran/dev_hf_cov_fixes
silabs-robin Sep 14, 2023
c553e7a
Updated default LFSR-coeffs/seed to ensure that these are not configu…
silabs-hfegran Sep 15, 2023
67c94c9
Merge pull request #2203 from silabs-hfegran/dev_hf_lfsr_seed
silabs-robin Sep 18, 2023
1952d64
Merge pull request #2177 from silabs-krdosvik/req_fifo
silabs-hfegran Sep 18, 2023
e0aa57c
Updated hpmcounter tests to account for csr stall optimizations
silabs-hfegran Sep 18, 2023
18cafe7
Merge pull request #2204 from silabs-hfegran/dev_hf_hpmcounter_fix
silabs-robin Sep 18, 2023
cabf6c3
Fixed unreachable cover
silabs-hfegran Sep 19, 2023
0f5820d
Merge pull request #2205 from silabs-hfegran/dev_hf_unr_fix
silabs-robin Sep 19, 2023
7836e63
Disabled assertion that frequently gives false posistives in sim, nee…
silabs-hfegran Sep 19, 2023
ff6bf34
Merge pull request #2207 from silabs-hfegran/dev_hf_ifault_asrt_dis
silabs-robin Sep 19, 2023
5258b35
Merge pull request #2158 from silabs-robin/debug_vplan
silabs-robin Sep 19, 2023
6e02d37
Disabled more buserr sb assertion
silabs-hfegran Sep 22, 2023
959aeb1
more xsecure expression coverage waving
silabs-krdosvik Sep 22, 2023
69d6096
Merge pull request #2209 from silabs-hfegran/dev_hf_fix_buserr_sb_dis…
silabs-robin Sep 22, 2023
2306dfb
Merge pull request #2210 from silabs-krdosvik/ccover_s
silabs-robin Sep 22, 2023
df28d57
exclude rest of xsecure code
silabs-krdosvik Sep 25, 2023
25550d0
Merge branch 'cv32e40s/dev' of github.com:openhwgroup/core-v-verif in…
silabs-krdosvik Sep 25, 2023
e8e91ae
Explicitly clear minhv at the end of mret_after_minhv test
silabs-hfegran Sep 25, 2023
2e0b55a
Merge pull request #2212 from silabs-hfegran/dev_hf_clear_minhv_clic_…
silabs-robin Sep 26, 2023
8308b7e
create cfg for external param sets
silabs-robin Sep 25, 2023
cdc1dc8
Merge pull request #2213 from silabs-robin/paramset
silabs-robin Sep 26, 2023
5ab1e75
Added minhv clear to reset_interrupt_level function for robustness
silabs-hfegran Sep 27, 2023
64fefe1
seperate code cover expression for xsecure and triggers, remove unnec…
silabs-krdosvik Sep 27, 2023
15290a0
changed comment about nmi integrity bit
silabs-krdosvik Sep 28, 2023
fe710cb
cov: re-enable toggle coverage
silabs-robin Sep 28, 2023
3129e23
Use naming convention, undo changes also stored in the xsecure_trigge…
silabs-krdosvik Sep 28, 2023
03055c2
Added cfg to disable data independent timing and pc hardening
silabs-hfegran Sep 28, 2023
6462d31
Merge pull request #2216 from silabs-krdosvik/ccover_s
silabs-robin Sep 28, 2023
2b45e37
Bugfix for enable/disable xsecure features
silabs-hfegran Sep 28, 2023
210005d
Merge pull request #2215 from silabs-hfegran/dev_hf_clear_minhv_clic_…
silabs-robin Sep 29, 2023
412173a
Merge pull request #2219 from silabs-hfegran/dev_hf_dis_xsec
silabs-robin Sep 29, 2023
b24f0fe
Enabled wfe_test and xsecure_* tests in full regression
silabs-hfegran Oct 3, 2023
33a0d70
Merge pull request #2223 from silabs-hfegran/dev_hf_regress_wfe_xsec
silabs-robin Oct 3, 2023
3ac5ef6
Removed tdata3 cover properties
silabs-hfegran Oct 3, 2023
cb2b643
Fixed isacov rd/rs-issues for zb* instructions (ISA_DECODER only)
silabs-hfegran Oct 3, 2023
9bcdc6f
Merge pull request #2226 from silabs-hfegran/dev_isacov_fix_rdrs
silabs-robin Oct 3, 2023
11bca14
Sync'ed naming convention between isacov and disassembler to fix cove…
silabs-hfegran Oct 3, 2023
63a8ef3
Merge pull request #2227 from silabs-hfegran/dev_isacov_fix_naming_conv
silabs-robin Oct 3, 2023
d048a73
Merge pull request #2217 from silabs-robin/togglecov
silabs-hfegran Oct 6, 2023
f232742
fencei_assert: relocate file
silabs-robin Oct 10, 2023
c8a63bb
fv: remove assert off default define
silabs-robin Oct 10, 2023
3a66c32
add 'assert off' to binds
silabs-robin Oct 10, 2023
7593489
Merge remote-tracking branch 'robin/assert_off' into branch_after_retire
silabs-robin Oct 11, 2023
c359006
remove comment about already removed code, fix xsecure prefix
silabs-krdosvik Oct 11, 2023
c5302e0
exempt certain modules from 'assert off'
silabs-robin Oct 11, 2023
24468d0
fencei_assert: start rewrite of 'branch_after_retire'
silabs-robin Oct 11, 2023
cc336a3
Merge remote-tracking branch 'robin/assert_off' into branch_after_retire
silabs-robin Oct 11, 2023
d3a5c4c
fencei_assert: rewrite 'branch_after_retire'
silabs-robin Oct 11, 2023
57ba371
Merge pull request #2233 from silabs-robin/assert_off
silabs-hfegran Oct 12, 2023
7683f76
fencei_assert: conform to coding guidelines interface instance suffix
silabs-robin Oct 12, 2023
159e393
Merge pull request #2234 from silabs-krdosvik/fix_comment
silabs-robin Oct 12, 2023
651d10b
Merge pull request #2235 from silabs-robin/branch_after_retire
silabs-hfegran Oct 12, 2023
723dda0
add 'cov_holes_generic' to the 'full' regression
silabs-robin Oct 12, 2023
dc0aa35
Added u-mode and mstatus.tw to wfe test, cleanup
silabs-hfegran Oct 13, 2023
5bd75aa
Fix stack corruption, add wfi+mstatus.tw in umode test, cleanup
silabs-hfegran Oct 13, 2023
be4c631
write secureseed x0 cov holes test
silabs-robin Oct 13, 2023
e8c73d6
write secureseed lockup cov holes test
silabs-robin Oct 13, 2023
b8a06d3
Merge pull request #2193 from silabs-robin/json_vplans_generation
silabs-hfegran Oct 16, 2023
e52ab0a
Merge pull request #2237 from silabs-hfegran/dev_hf_wfe_test_updates
silabs-robin Oct 16, 2023
d17af14
Update clic test to cover verification holes wrt. illegal mnxti accesses
silabs-hfegran Oct 16, 2023
ab123e1
Merge pull request #2246 from silabs-hfegran/dev_hf_clic_test_mnxti_u…
silabs-robin Oct 16, 2023
e85c491
Clic test hotfix - wrong expect-illegal handling in ex.handler
silabs-hfegran Oct 16, 2023
309e400
Merge pull request #2247 from silabs-hfegran/dev_hf_clic_test_hotfix
silabs-robin Oct 16, 2023
e7de5f9
Updated link to coverage
silabs-mateilga Oct 17, 2023
dd4be48
Added PMP CSR write test to aid coverage closure
silabs-hfegran Oct 17, 2023
10b378e
Moved bitfield defines to correct section
silabs-hfegran Oct 17, 2023
d5fca75
Merge pull request #2249 from silabs-hfegran/dev_hf_pmp_csr_test
silabs-robin Oct 17, 2023
64720c2
start pushpop triggers test
silabs-robin Oct 17, 2023
cf3f38c
test push debug triggers
silabs-robin Oct 17, 2023
6a680b8
review feedback
silabs-mateilga Oct 18, 2023
a22ed4d
Added compressed csr-representation to isa decoder, and updated isaco…
silabs-hfegran Oct 18, 2023
cc35f7d
test pop debug triggers
silabs-robin Oct 18, 2023
9d39f43
move pushpop test to standalone
silabs-robin Oct 18, 2023
2397993
Merge pull request #2248 from silabs-mateilga/zc_vplan_update
silabs-robin Oct 19, 2023
24e9ad2
Merge pull request #2253 from silabs-robin/wpt_pushpop
silabs-robin Oct 19, 2023
2e90d8c
merge 'secureseed' test into 'xsecure_csrs' test
silabs-robin Oct 19, 2023
fd3618a
Merge branch 'cv32e40s/dev' of github.com:openhwgroup/core-v-verif in…
silabs-robin Oct 19, 2023
70800b4
add vplan item for future complete checking of lfsr lockup
silabs-robin Oct 19, 2023
8c344c0
add comment about missing lfsr lockup check
silabs-robin Oct 20, 2023
30cdc51
Merge pull request #2239 from silabs-robin/secureseed
silabs-hfegran Oct 20, 2023
62b3768
Name changes to compressed register representations
silabs-hfegran Oct 20, 2023
f494abd
Another name change, cleanup, add default case
silabs-hfegran Oct 20, 2023
3470297
Merge pull request #2251 from silabs-hfegran/dev_hf_isa_decoder_fix
silabs-robin Oct 20, 2023
538a401
Added flag to prevent xcelium from searching for cds.lib/hdl.var unle…
silabs-hfegran Oct 23, 2023
457d2e9
Updated wfe test to work correctly without user-mode/PMP, added flags…
silabs-hfegran Oct 23, 2023
e6db7d8
Reverted ISS flag as it appeared to have no effect
silabs-hfegran Oct 23, 2023
99767cd
Merge pull request #2254 from silabs-hfegran/dev_hf_nocsf_flag
silabs-robin Oct 23, 2023
7c2a400
Merge pull request #2255 from silabs-hfegran/dev_hf_wfe_test_updates
silabs-robin Oct 23, 2023
af0b537
Merge branch 'cv32e40s/dev' of github.com:silabs-hfegran/core-v-verif
silabs-hfegran Oct 23, 2023
a45b7ea
Fix merge conflicts
silabs-hfegran Oct 23, 2023
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Fixed issue where clic tests would fail due to (unintended) too high …
…mintstatus.mil level

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>
  • Loading branch information
silabs-hfegran committed Jul 27, 2023
commit 7e80632be764ea91896cff3de545479b505aada4
82 changes: 76 additions & 6 deletions cv32e40s/tests/programs/custom/clic/clic.c
Original file line number Diff line number Diff line change
@@ -341,10 +341,20 @@ void set_mseccfg(mseccfg_t mseccfg);
/*
* increment_mepc
*
* TODO
* Increments mepc,
* incr_val 0 = auto detect
* 2 = halfword
* 4 = word
*/
void increment_mepc(uint32_t incr_val);

/*
* reset_cpu_interrupt_lvl
*
* Resets core internal interrupt level (as reported by mintsstatus.mil)
*/
void reset_cpu_interrupt_lvl(void);

// ---------------------------------------------------------------
// Test entry point
// ---------------------------------------------------------------
@@ -2723,9 +2733,41 @@ uint32_t mret_with_minhv(uint32_t index, uint8_t report_name) {

// -----------------------------------------------------------------------------

void reset_cpu_interrupt_lvl(void) {
volatile mcause_t mcause = { 0 };
volatile mstatus_t mstatus = { 0 };
volatile uint32_t pc = 0;

__asm__ volatile ( R"(
csrrs %[mstatus], mstatus, zero
csrrs %[mcause], mcause, zero
)":[mstatus] "=r"(mstatus.raw),
[mcause] "=r"(mcause.raw)
::);

mcause.clic.mpil = 0;
mcause.clic.mpie = mstatus.fields.mie;
mcause.clic.mpp = 0x3;

__asm__ volatile ( R"(
la %[pc], continued
csrrw zero, mcause, %[mcause]
csrrw zero, mepc, %[pc]
mret
continued:
nop
)":[pc] "+r"(pc)
:[mcause] "r"(mcause.raw)
:);
return;
}

// -----------------------------------------------------------------------------

uint32_t mintthresh_lower(uint32_t index, uint8_t report_name) {
volatile uint8_t test_fail = 0;
volatile mintthresh_t mintthresh = { 0 };
volatile mintstatus_t mintstatus = { 0 };
volatile uint32_t mnxti_rval = 0;
volatile clic_t clic_irq_vector = { 0 };

@@ -2737,10 +2779,20 @@ uint32_t mintthresh_lower(uint32_t index, uint8_t report_name) {

mintthresh.fields.th = 0xff;
*g_special_handler_idx = 4;

__asm__ volatile (R"(csrrs %[rd], 0xfb1, zero)":[rd] "=r"(mintstatus.raw));
// To be potentially set by handler if incorrectly entered
*g_irq_handler_reported_error = 0;

*g_asserted_irq_idx = get_random_interrupt_number(0, NUM_INTERRUPTS);
*g_asserted_irq_lvl = get_random_interrupt_level(0, NUM_INTERRUPT_LVLS-1);

// Random interrupt with higher level than core, but lower than mintthresh;
*g_asserted_irq_lvl = get_random_interrupt_level(mintstatus.fields.mil + 1, NUM_INTERRUPT_LVLS-1);

if (*g_asserted_irq_lvl <= mintstatus.fields.mil) {
// Reset cpu interrupt level, as we cannot not reach our desired test case
reset_cpu_interrupt_lvl();
}

cvprintf(V_DEBUG, "mintthresh.th: %01x, interrupt: %02x, level: %02x\n", mintthresh.fields.th, *g_asserted_irq_idx, *g_asserted_irq_lvl);

@@ -2788,10 +2840,11 @@ uint32_t mintthresh_lower(uint32_t index, uint8_t report_name) {

uint32_t mintthresh_higher(uint32_t index, uint8_t report_name) {
volatile uint8_t test_fail = 0;
volatile mintthresh_t mintthresh = { 0 };
volatile uint32_t mnxti_rval = 0;
volatile clic_t clic_irq_vector = { 0 };
volatile uint32_t mtvt = 0;
volatile mintthresh_t mintthresh = { 0 };
volatile mintstatus_t mintstatus = { 0 };
volatile clic_t clic_irq_vector = { 0 };

SET_FUNC_INFO
if (report_name) {
@@ -2800,12 +2853,20 @@ uint32_t mintthresh_higher(uint32_t index, uint8_t report_name) {
}

*g_special_handler_idx = 5;

__asm__ volatile (R"(csrrs %[rd], 0xfb1, zero)":[rd] "=r"(mintstatus.raw));

// To be cleared by handler
*g_irq_handler_reported_error = 1;
mintthresh.fields.th = get_random_interrupt_level(1, NUM_INTERRUPT_LVLS-1);
*g_asserted_irq_idx = get_random_interrupt_number(1, NUM_INTERRUPTS);
*g_asserted_irq_lvl = get_random_interrupt_level(mintthresh.fields.th + 1, NUM_INTERRUPT_LVLS);

if (*g_asserted_irq_lvl <= mintstatus.fields.mil) {
// Reset cpu interrupt level, as we cannot not reach our desired test case
reset_cpu_interrupt_lvl();
}

cvprintf(V_DEBUG, "mintthresh.th: %01x, interrupt: %02x, level: %02x\n", mintthresh.fields.th, *g_asserted_irq_idx, *g_asserted_irq_lvl);

vp_assert_irq(0, 0);
@@ -2824,7 +2885,7 @@ uint32_t mintthresh_higher(uint32_t index, uint8_t report_name) {
.fields.shv = 0x0
};

// asserted interrupt should not be taken (mintthresh.th too high)
// asserted interrupt should be taken (mintthresh.th low enough)
vp_assert_irq(clic_irq_vector.raw, 0);

__asm__ volatile ( R"(
@@ -2852,8 +2913,9 @@ uint32_t mintthresh_higher(uint32_t index, uint8_t report_name) {

uint32_t mintthresh_equal(uint32_t index, uint8_t report_name) {
volatile uint8_t test_fail = 0;
volatile mintthresh_t mintthresh = { 0 };
volatile uint32_t mnxti_rval = 0;
volatile mintthresh_t mintthresh = { 0 };
volatile mintstatus_t mintstatus = { 0 };
volatile clic_t clic_irq_vector = { 0 };

SET_FUNC_INFO
@@ -2863,12 +2925,20 @@ uint32_t mintthresh_equal(uint32_t index, uint8_t report_name) {
}

*g_special_handler_idx = 6;

__asm__ volatile (R"(csrrs %[rd], 0xfb1, zero)":[rd] "=r"(mintstatus.raw));

// To be set by handler in case of entry
*g_irq_handler_reported_error = 0;
mintthresh.fields.th = get_random_interrupt_level(1, NUM_INTERRUPT_LVLS);
*g_asserted_irq_idx = get_random_interrupt_number(1, NUM_INTERRUPTS);
*g_asserted_irq_lvl = mintthresh.fields.th;

if (*g_asserted_irq_lvl <= mintstatus.fields.mil) {
// Reset cpu interrupt level, as we cannot not reach our desired test case
reset_cpu_interrupt_lvl();
}

cvprintf(V_DEBUG, "mintthresh.th: %01x, interrupt: %02x, level: %02x\n", mintthresh.fields.th, *g_asserted_irq_idx, *g_asserted_irq_lvl);

vp_assert_irq(0, 0);