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    294 repositories

    • carfield

      Public
      A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
      casicfpgasimulationriscvsystemverilogsafety-criticalheterogeneous-computingmixed-criticality-systems
      Tcl
      •
      Other
      •14•77•16•6•Updated Jan 15, 2025Jan 15, 2025

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •52•216•8•17•Updated Jan 15, 2025Jan 15, 2025

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •134•391•64•8•Updated Jan 15, 2025Jan 15, 2025

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •34•39•6•4•Updated Jan 15, 2025Jan 15, 2025

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •707•17•0•5•Updated Jan 15, 2025Jan 15, 2025

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •21•64•4•4•Updated Jan 15, 2025Jan 15, 2025

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •148•550•31•8•Updated Jan 15, 2025Jan 15, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •18•83•1•2•Updated Jan 14, 2025Jan 14, 2025

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •10•20•4•2•Updated Jan 14, 2025Jan 14, 2025

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •11•12•3•4•Updated Jan 13, 2025Jan 13, 2025

    • occamy

      Public
      A high-efficiency system-on-chip for floating-point compute workloads.
      Python
      •
      Apache License 2.0
      •14•21•7•1•Updated Jan 13, 2025Jan 13, 2025

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •58•58•15•7•Updated Jan 13, 2025Jan 13, 2025

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •67•1•0•2•Updated Jan 10, 2025Jan 10, 2025

    • opensbi

      Public
      RISC-V Open Source Supervisor Binary Interface
      C
      •
      Other
      •529•0•0•2•Updated Jan 10, 2025Jan 10, 2025

    • chimera

      Public
      Python
      •
      Other
      •2•13•9•1•Updated Jan 9, 2025Jan 9, 2025

    • chimera-sdk

      Public
      Python
      •
      Apache License 2.0
      •3•3•6•3•Updated Jan 9, 2025Jan 9, 2025

    • CHERI-Litmus

      Public
      A tool to run litmus tests on bare-metal hardware
      C
      •
      Other
      •12•2•0•1•Updated Jan 9, 2025Jan 9, 2025

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •6•43•0•0•Updated Jan 8, 2025Jan 8, 2025

    • pulp-riscv-gnu-toolchain

      Public
      C
      •
      Other
      •52•74•25•0•Updated Jan 8, 2025Jan 8, 2025

    • pulp-riscv-binutils-gdb

      Public
      C
      •
      Other
      •21•0•2•4•Updated Jan 8, 2025Jan 8, 2025

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •29•114•7•5•Updated Jan 7, 2025Jan 7, 2025

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •273•1.2k•44•9•Updated Jan 7, 2025Jan 7, 2025

    • common_verification

      Public
      SystemVerilog modules and classes commonly used for verification
      SystemVerilog
      •
      Other
      •14•44•0•2•Updated Jan 7, 2025Jan 7, 2025

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •47•280•3•4•Updated Jan 7, 2025Jan 7, 2025

    • svase

      Public
      C++
      •
      Apache License 2.0
      •2•31•1•0•Updated Jan 7, 2025Jan 7, 2025

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •14•5•0•6•Updated Jan 7, 2025Jan 7, 2025

    • ManyRVData

      Public
      0•0•0•0•Updated Jan 7, 2025Jan 7, 2025

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •15•21•3•9•Updated Jan 6, 2025Jan 6, 2025

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •117•12•0•4•Updated Jan 3, 2025Jan 3, 2025

    • memory_island

      Public
      An interleaved high-throughput low-contention L2 scratchpad memory.
      SystemVerilog
      •
      Other
      •2•2•4•3•Updated Jan 3, 2025Jan 3, 2025