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Add -no_sat and -init_registers synth_options #2108

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Dec 2, 2024
Merged

Add -no_sat and -init_registers synth_options #2108

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4bf641d
New synth_options -no_sat and -init_registers
ravikiranchollangi Dec 1, 2024
334addf
Add init_registers to GUI settings
ravikiranchollangi Dec 2, 2024
fcd4449
Update foedag_rs
ravikiranchollangi Dec 2, 2024
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2 changes: 1 addition & 1 deletion FOEDAG_rs
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Submodule FOEDAG_rs updated 5 files
+1 −1 FOEDAG
+342 −337 etc/help.txt
+72 −8 etc/settings/settings_test.json
+45 −7 src/Compiler/CompilerRS.cpp
+8 −0 src/Compiler/CompilerRS.h
11 changes: 6 additions & 5 deletions README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -139,11 +139,12 @@ Tcl commands (Available in GUI or Batch console or Batch script):
-no_adder : Do not infer adders
-inferred_io : Automatic I/O inference (Default false for eFPGA)
-no_inferred_io : No automatic I/O inference (Default true for FPGA)
-read_init_registers <int> : Force initialization to uninitialized registers (0, 1, 2)
0 : Initialize register by '0' (default)
1 : Initialize register by '1'
2 : Leave register unintialized
set_limits <type> <int> : Sets a user limit on object of type (dsp, bram), specify 0 to disable block inferrence
-no_sat : Disable SAT solver
-init_registers <int> : Force initialization of uninitialized registers
0 : '0' value means initialize with '0' (Default '0' is used)
1 : '1' value means initialize with '1'
2 : '2' value means leave it uninitialized
set_limits <type> <int> : Sets a user limit on object of type (dsp, bram), specify 0 to disable block inferrence
dsp : Maximum number of usable DSPs
bram : Maximum number of usable BRAMs
carry_length : Maximum carry length
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10 changes: 5 additions & 5 deletions etc/help.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -130,11 +130,11 @@ Tcl commands (Available in GUI or Batch console or Batch script):
-no_adder : Do not infer adders
-inferred_io : Automatic I/O inference (Default false for eFPGA)
-no_inferred_io : No automatic I/O inference (Default true for FPGA)
-read_init_registers <int> : Force initialization to uninitialized registers (0, 1, 2)
0 : Initialize register by '0' (default)
1 : Initialize register by '1'
2 : Leave register unintialized
<engineering>
-no_sat : Disable SAT solver
-init_registers <int> : Force initialization of uninitialized registers
0 : '0' value means initialize with '0' (Default '0' is used)
1 : '1' value means initialize with '1'
2 : '2' value means leave it uninitialized<engineering>
-clke_strategy <strategy>: Clock enable extraction strategy for FFs:
early : Perform early extraction
late : Perform late extraction
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13 changes: 13 additions & 0 deletions etc/settings/settings_test.json
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Expand Up @@ -120,6 +120,19 @@
"stepVal": 1,
"arg": "carry_chain_limit"
},
"init_registers_spinbox_ex": {
"label": "Init Registers",
"widgetType": "spinbox",
"minVal": 0,
"maxVal": 2,
"stepVal": 1,
"arg": "init_registers"
},
"no_sat_checkbox": {
"label": "No Sat",
"widgetType": "checkbox",
"arg": "no_sat"
},
"fast_checkbox": {
"label": "Fast Synthesis",
"widgetType": "checkbox",
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