Skip to content

PZCOREBUS Protocol Specification

Jump to bottom
Taichi Ishitani edited this page Apr 14, 2023 · 14 revisions

PZCOREBUS Protocol Specification

Overview

PZOREBUS is a bus protocol designed for use in a SoC design to connect master and slave components. PZCOREBUS has following features:

  • supports both of high-performance memory access and registrer access
  • uses burst based transactions
  • supports issuing multiple outstanding accesses
  • supports out-of-order transaction completion
  • supports read data interleaving

Architecture

Channels

PZCOREBUS is burst-based and defines three independent channels.

  • mcmd channel
    • transmits a set of request information such as command type, address, length, etc
  • mdata channel
    • transmits write data
  • sresp channel
    • transmits read data response and acknowledgement response

Profile

PZCOREBUS defines three profiles according to usage.

  • PZCOREBUS_MEMORY_H
  • PZCOREBUS_MEMORY_C
  • PZCOREBUS_CSR

PZCOREBUS_MEMORY_H

This profile is for high-performance memory access and has following features.

  • supprots multi-burst access
  • supports narrow access
  • supports read data interleaving
  • supports data bus width conversion

PZCOREBUS_MEMORY_L

This profile is limitaed version of PZCOREBUS_MEMORY_H profile. For simplification, Following limitations are introduced.

  • not supports narrow access
  • not supports read data interleaving
  • not supports data bus width conversion

PZCOREBUS_CSR

This profile is for register access. Following limitations are introduced for simplification.

  • supports single burst access only
  • transmits write data via mcmd channel
    • not uses mdata channel
  • not supports byte eanble
  • supports following commands only
    • PZCOREBUS_READ
    • PZCOREBUS_WRITE
    • PZCOREBUS_WRITE_NON_POSTED
    • PZCOREBUS_BROADCAST

Interface Descriptions

Handshake Process

All three channels use the valid/accept handshake process to transfer information attached to each channels. The source component drives the valid signal high to indicate when information being transfered is active. The destination component the accept signal high to indicate that it can accept the information. Information transfer is completed only when valid and accept signals are high. When the source component asserts the valid high, it must keep the valid signal and the related information stable until a handshake process is completed.

In addition, to prevent a deadlock situation, there are dependencies between valid and ready signals:

  • the source component must not wait for the ready signal to be asserted high before asserting the valid signal high
  • the destination component can wait for the valid signal to be asserted high before asserting the ready signal high

Prameters

Some interface singals are parameterized by parameters described below.

  • id_width
    • specifies width of transaction id
  • address_width
    • specifies width of address
  • data_width
    • specified width of write/data
    • must be larger than or equal to 8 and be power of 2
  • max_length
    • specified maximum length of a transaction
    • is valid for PZCOREBUS_MEMORY_H/PZCOREBUS_MEMORY_L profile
    • unit of length is specified by
      • unit_data_width in case of PZCOREBUS_MEMORY_H profile
      • data_width in case of PZCOREBUS_MEMORY_L profile
  • request_info_width
    • specifies width of sideband information attached with mcmd channel
    • width 0 is allowed when the sideband information is not required
  • response_info_width
    • specifies width of sideband information attached with sresp channel
    • width 0 is allowed when the sideband information is not required
  • unit_data_width
    • specifies unit size of data transfer
    • is valid for PZCOREBUS_MEMORY_H profile
  • max_data_width
    • specifies the maximum data width across the bus interconnect
    • is valid for PZCOREBUS_MEMORY_H profile

Signal Descriptions

mcmd channel

The table below shows mcmd channel signals.

name width driver
scmd_accept 1 slave
mcmd_valid 1 master
mcmd 4 master
mid id_width master
maddr address_width master
mlength clog2(max_length) master
mdata data_width master
minfo request_info_width master
scmd_accept

Indicates that the slave component can accept the given request information

mcmd_valid

Indicates that the master component is offering a valid request information

mcmd

Indicate the command of the request. Commands are enconded as follows.

command mcmd with payload (mcmd[3]) non-posted (mcmd[2]) kind (mcmd[2:0])
PZCOREBUS_READ 0b01_001 0 1 0x1
PZCOREBUS_WRITE 0b10_010 1 0 0x2
PZCOREBUS_WRITE_NON_POSTED 0b11_010 1 1 0x2
PZCOREBUS_FULL_WRITE 0b10_011 1 0 0x3
PZCOREBUS_FULL_WRITE_NON_POSTED 0b10_011 1 0 0x3
PZCOREBUS_BROADCAST 0b10_100 1 0 0x4
PZCOREBUS_BROADCAST_NON_POSTED 0b10_100 1 1 0x4
PZCOREBUS_ATOMIC 0b10_101 1 0 0x5
PZCOREBUS_ATOMIC_NON_POSTED 0b11_101 1 1 0x5
PZCOREBUS_MESSAGE 0b00_110 0 0 0x6
PZCOREBUS_MESSAGE_NON_POSTED 0b01_110 0 1 0x6
mid

Indicate the transaction id of the request.

maddr

Indicates the target byte address of the request.

mlength

For PZCOREBUS_READ, PZCOREBUS_WRITE, PZCOREBUS_WRITE_NON_POSTED and PZCOREBUS_BROADCAST, indicates how many data bytes need to be transferred. Number of transferred bytes is calculated as follows.

  • For PZCOREBUS_MEMORY_H profile:
    • when mlength is not 0
      • data bytes = (unit_data_width / 8) * mlength
    • when mlength is 0
      • data bytes = (unit_data_width / 8) * max_length
  • For PZCOREBUS_MEMORY_L profile:
    • mlength acts as burst length
    • when mlength is not 0
      • data bytes = (data_width / 8) * mlength
    • when mlength is 0
      • data bytes = (data_width / 8) * max_length
  • For PZCOREBUS_CSR profile:
    • mlength is not valid for this profile
    • data byte = data_width / 8

For PZCOREBUS_ATOMIC and PZCOREBUS_ATOMIC_NON_POSTED, mlength is not valid for these commands.

For PZCOREBUS_MESSAGE and PZCOREBUS_MESSAGE_NON_POSTED, mlength contains information sent from the master component to the target slave component. This specification does not specify its format.

mdata

Write data for the request. This filed is valid only for PZCOREBUS_CSR profile.

minfo

Sideband information for the request. This field is valid only when the request_info_width parameter is > 0.

mdata channel

The table below shows mcmd channel signals. The mdata channels is valid for PZCOREBUS_MEMORY_H and PZCOREBUS_MEMORY_L profiles.

name width driver
sdata_accept 1 slave
mdata_valid 1 master
mdata data_width master
mdata_byteen data_width/8 master
mdata_last 1 master
sdata_accept

Indicates the slave component can accept the given write data.

mdata_valid

Indicate the master component is offering a valid write data.

mdata

Write data for the request.

mdata_byteen

Indicates the corresponding byte lane holds a valid write data.

mdata_last

Indicates the current write data is the last write data for the request. After that, no write data for the same request will be transferred.

sresp channel

The table below shows sresp channel signals.

name width driver
mresp_accept 1 master
sresp_valid 1 slave
sresp 1 slave
sid id_width slave
serror 1 slave
sdata data_width slave
sinfo response_info_width slave
sresp_uniten max_data_width/unit_data_width slave
sresp_last 1 or 2 slave
mresp_accept

Indicates the master component can accept the given response.

sresp_valid

Indicates the slave component is offering a valid response.

sresp

Indicates the type of the response. Response types are encoded as follows.

type value description
PZCOREBUS_RESPONSE 0b0 Response without data payload
PZCOREBUS_RESPONSE_WITH_DATA 0b1 Response with data payload
sid

Indicate the transaction id of the response.

serror

Indicates the corresponding request was not be served successfully.

sdata
  • When the corresponding request is PZCOREBUS_READ sdata contains read data.
  • When the corresponding request is PZCOREBUS_ATOMIC_NON_POSTED sdata contains the result of the ATOMIC operation.
sinfo

Sideband information for the response. This field is valid only when the response_info_width parameter is > 0.

sresp_uniten

Indicates the corresponding data unit lane contains a valid read data. This field is valid only for PZCOREBUS_MEMORY_H profile.

sresp_last

sresp_last[0] indicates the current response is the last response of the corresponding request. After that, no response for the same request will be transfered. sresp_last[0] is valid for PZCOREBUS_MEMORY_H and PZCOREBUS_MEMORY_L profiles.

sresp_last[1] indicates the current response is the tail of sequence of responses for the curresponding request. The slave component will re-start sending responses for the same request after an arbitrarily delay. sresp_last[1] is valid only for PZCOREBUS_MEMORY_H profile.

Data Write/Read Structure

For PZCOREBUS_MEMORY_H Profile

Range of valid data is represented by maddr and mlength fields:

  • start index on the data bus:
    • start_index = maddr[clog2(data_width/8)-1:clog2(unit_data_width/8)]
  • transfer data size:
    • mlength

Therefore, number of data transfers (burst_length) is caluculated as follow.

  • burst_length = (start_index + mlength + (data_width / unit_data_width) - 1) / (data_width / unit_data_width)

For ease of implementing data bus width conversion modules, sresp_uniten field is introduced to the sresp channel. This field indicates which unit data lanes are valid within max_data_width.

Clone this wiki locally