hw: Add SMP support to boot ROM #58
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- Pause all harts except 0 at the beginning of the bootrom - Let all harts jump to next boot stage after hart 0 finished bootrom - Park all harts except 0 at the beginning of crt0 for now (to be extended) - Increase number of scratch registers from 4 to 16 (e.g. for boot address synchronisation) Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
paulsc96
previously approved these changes
Aug 2, 2023
alex96295
previously approved these changes
Aug 3, 2023
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Fixes the MISP register layout Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
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MaistoV
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Aug 23, 2023
* bootrom: Support SMP - Pause all harts except 0 at the beginning of the bootrom - Let all harts jump to next boot stage after hart 0 finished bootrom - Park all harts except 0 at the beginning of crt0 for now (to be extended) - Increase number of scratch registers from 4 to 16 (e.g. for boot address synchronisation) Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> * bootrom: Parametrise number of harts via cheshire_regs Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> * bootrom: Load word unsigned Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> * bootrom: Fix smp_resume jump target Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> * ci: Bump cheshire-nonfree Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> * clint: Bump v0.2.0 Fixes the MISP register layout Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> * clint.h: Update Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> --------- Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
mattsini1
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Aug 30, 2023
* bootrom: Support SMP - Pause all harts except 0 at the beginning of the bootrom - Let all harts jump to next boot stage after hart 0 finished bootrom - Park all harts except 0 at the beginning of crt0 for now (to be extended) - Increase number of scratch registers from 4 to 16 (e.g. for boot address synchronisation) Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> * bootrom: Parametrise number of harts via cheshire_regs Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> * bootrom: Load word unsigned Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> * bootrom: Fix smp_resume jump target Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> * ci: Bump cheshire-nonfree Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> * clint: Bump v0.2.0 Fixes the MISP register layout Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> * clint.h: Update Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> --------- Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Aquaticfuller
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Jul 16, 2024
Decouple HW, SW and simulation build targets
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Add SMP support in the bootrom. In particular,
0at the beginning of the bootrom,0finished bootrom,0at the beginning of crt0 for now (to be extended).To facilitate this,