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@riscv-non-isa

RISC-V Non-ISA Specifications

The Open-Standard Instruction Set Architecture

Welcome to the RISC-V Non-ISA Specifications 👋

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Non-ISA specifications do not add new instructions, create or change opcodes, or in any way modify the RISC-V ISA. They do help us to develop an ecosystem around the ISA Specifications.

Things you'll find here include:

  • ABI Documentation
  • Architecture Tests
  • Specifications like Debug, Processor Trace, and Software Interrupts

If you don't find what you're looking for here, try one of our other GitHub organizations:

Popular repositories Loading

  1. riscv-asm-manual riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    Makefile 1.5k 239

  2. riscv-elf-psabi-doc riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    Python 725 165

  3. riscv-arch-test riscv-arch-test Public

    Assembly 527 209

  4. riscv-sbi-doc riscv-sbi-doc Public

    Documentation for the RISC-V Supervisor Binary Interface

    Makefile 358 94

  5. rvv-intrinsic-doc rvv-intrinsic-doc Public

    C 302 90

  6. riscv-trace-spec riscv-trace-spec Public

    RISC-V Processor Trace Specification

    C 169 48

Repositories

Showing 10 of 35 repositories
  • riscv-ap-tee Public

    This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the programming interfaces (ABI) to support the Confidential VM Extension (CoVE) confidential computing architecture for RISC-V application-processor platforms.

    riscv-non-isa/riscv-ap-tee’s past year of commit activity
    Makefile 51 CC-BY-4.0 22 25 0 Updated Jan 2, 2025
  • riscv-rpmi Public

    RISC-V Platform Management Interface Specification. OS-agnostic messaging interface for system management and control

    riscv-non-isa/riscv-rpmi’s past year of commit activity
    Makefile 8 CC-BY-4.0 9 1 2 Updated Jan 2, 2025
  • riscv-non-isa/riscv-arch-test’s past year of commit activity
    Assembly 527 Apache-2.0 209 45 32 Updated Jan 1, 2025
  • riscv-iommu Public

    RISC-V IOMMU Specification

    riscv-non-isa/riscv-iommu’s past year of commit activity
    C 101 CC-BY-4.0 18 1 2 Updated Dec 25, 2024
  • riscv-trace-spec Public

    RISC-V Processor Trace Specification

    riscv-non-isa/riscv-trace-spec’s past year of commit activity
    C 169 CC-BY-4.0 48 25 14 Updated Dec 23, 2024
  • riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    riscv-non-isa/riscv-asm-manual’s past year of commit activity
    Makefile 1,456 CC-BY-4.0 239 6 7 Updated Dec 20, 2024
  • iopmp-spec Public

    This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.

    riscv-non-isa/iopmp-spec’s past year of commit activity
    Makefile 17 CC-BY-4.0 6 1 1 Updated Dec 20, 2024
  • riscv-c-api-doc Public

    Documentation of the RISC-V C API

    riscv-non-isa/riscv-c-api-doc’s past year of commit activity
    Makefile 74 CC-BY-4.0 42 17 9 Updated Dec 19, 2024
  • riscv-toolchain-conventions Public

    Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains

    riscv-non-isa/riscv-toolchain-conventions’s past year of commit activity
    Makefile 147 CC-BY-4.0 37 15 9 Updated Dec 18, 2024
  • riscv-cbqri Public

    This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register interface is a non-ISA specification that supports configuring resource allocations to applications and monitoring the resource usage by applications.

    riscv-non-isa/riscv-cbqri’s past year of commit activity
    Makefile 4 CC-BY-4.0 8 0 1 Updated Dec 18, 2024

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