Add DCSR.MPRVEN testing

debug/gdbserver.py

@@ -1791,6 +1791,42 @@ def test(self):
         self.gdb.p("vms=&sv48")
         self.test_translation()
 
+class HWTranslateTest(TranslateTest):
+    def test_hw_translation(self):
+        output = self.gdb.command("monitor riscv virt2phys_mode hw")
+        self.gdb.p(output)
+        self.test_translation()
+
+class Sv32HWTest(HWTranslateTest):
+    def early_applicable(self):
+        return TranslateTest.early_applicable(self) and \
+            self.hart.progbufsize and self.hart.xlen == 32
+
+    def test(self):
+        self.check_satp(SATP_MODE_SV32)
+        self.gdb.p("vms=&sv32")
+        self.test_hw_translation()
+
+class Sv39HWTest(HWTranslateTest):
+    def early_applicable(self):
+        return TranslateTest.early_applicable(self) and \
+            self.hart.progbufsize and self.hart.xlen > 32
+
+    def test(self):
+        self.check_satp(SATP_MODE_SV39)
+        self.gdb.p("vms=&sv39")
+        self.test_hw_translation()
+
+class Sv48HWTest(HWTranslateTest):
+    def early_applicable(self):
+        return TranslateTest.early_applicable(self) and \
+            self.hart.progbufsize and self.hart.xlen > 32
+
+    def test(self):
+        self.check_satp(SATP_MODE_SV48)
+        self.gdb.p("vms=&sv48")
+        self.test_hw_translation()
+
 class VectorTest(GdbSingleHartTest):
     compile_args = ("programs/vectors.S", )
 

debug/targets.py

@@ -56,13 +56,16 @@ class Hart:
     # Supports the cease instruction, which causes a hart to become unavailable.
     support_cease = False
 
-    def __init__(self, misa=None, system=None, link_script_path=None):
+    progbufsize = None
+
+    def __init__(self, misa=None, system=None, link_script_path=None, progbufsize=None):
         if misa:
             self.misa = misa
         if system:
             self.system = system
         if link_script_path:
             self.link_script_path = link_script_path
+        self.progbufsize = progbufsize
 
     def extensionSupported(self, letter):
         # target.misa is set by testlib.ExamineTarget

debug/targets/RISC-V/spike32-pb.py

@@ -0,0 +1,20 @@
+import spike32  # pylint: disable=import-error
+
+import targets
+import testlib
+
+class spike32_pb(targets.Target):
+    harts = [spike32.spike32_hart(misa=0x4034112d, progbufsize=6)]
+    openocd_config_path = "spike-1.cfg"
+    timeout_sec = 180
+    implements_custom_test = True
+    support_memory_sampling = False # Needs SBA
+    freertos_binary = "bin/RTOSDemo32.axf"
+    support_unavailable_control = True
+
+    def create(self):
+        # 64-bit FPRs on 32-bit target
+        return testlib.Spike(self, isa="RV32IMAFDCV", dmi_rti=4,
+                support_abstract_csr=True, support_haltgroups=False,
+                # elen must be at least 64 because D is supported.
+                elen=64, progbufsize=self.harts[0].progbufsize)

debug/targets/RISC-V/spike64-pb.py

@@ -0,0 +1,20 @@
+import spike64  # pylint: disable=import-error
+
+import targets
+import testlib
+
+class spike64(targets.Target):
+    harts = [spike64.spike64_hart(progbufsize=6)]
+    openocd_config_path = "spike-1.cfg"
+    timeout_sec = 180
+    implements_custom_test = True
+    freertos_binary = "bin/RTOSDemo64.axf"
+    support_unavailable_control = True
+
+    def create(self):
+        # 32-bit FPRs only
+        return testlib.Spike(self, isa="RV64IMAFC", 
+                progbufsize=self.harts[0].progbufsize,
+                abstract_rti=30, support_abstract_csr=True,
+                support_abstract_fpr=True)
+