Merge pull request #1806 from trdthg/fix-typos

Fix typos

src/b-st-ext.adoc

@@ -3671,7 +3671,7 @@ Included in::
 
 Synopsis::
 Interleave upper and lower halves of the source register into odd and even
-bits of the destination register, respectivley.
+bits of the destination register, respectively.
 
 Mnemonic::
 zip _rd_, _rs_

src/example/sgemm.S

@@ -78,7 +78,7 @@ c_col_loop: # Loop across one row of C blocks
     mv akp, ap   # reset pointer into A to beginning
     mv bkp, bnp # step to next column in B matrix
 
-    # Initalize current C submatrix block from memory.
+    # Initialize current C submatrix block from memory.
     vle32.v  v0, (cnp); add ccp, cnp, cstride;
     vle32.v  v1, (ccp); add ccp, ccp, cstride;
     vle32.v  v2, (ccp); add ccp, ccp, cstride;

src/machine.adoc

@@ -199,7 +199,7 @@ implementation may not support one or more of the Zba, Zbb, or Zbs extensions.
 When the "M" bit is 1, the implementation supports all multiply and
 division instructions defined by the M extension. When the "M" bit
 is 0, it indicates that the implementation may not support those
-instructions. However if the Zmmul extension is suppported then
+instructions. However if the Zmmul extension is supported then
 the multiply instructions it specifies are supported irrespective
 of the value of the "M" bit.
 

src/q-st-ext.adoc

@@ -77,7 +77,7 @@ FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to
 a double-precision floating-point number, or vice-versa, respectively.
 
 include::images/wavedrom/quad-cnvt-interchange.edn[]
-[[quad-convrt-interchange]]
+[[quad-convert-interchange]]
 //.Quad-precision convert and move interchangeably
 
 Floating-point to floating-point sign-injection instructions, FSGNJ.Q,

src/scalar-crypto.adoc

@@ -3464,7 +3464,7 @@ Included in::
 
 Synopsis::
 Interleave upper and lower halves of the source register into odd and even
-bits of the destination register, respectivley.
+bits of the destination register, respectively.
 
 Mnemonic::
 zip _rd_, _rs_
@@ -5323,7 +5323,7 @@ is recommended reading in order to best understand the supporting code.
 
 [source,sail]
 ----
-/* Auxiliary function for performing GF multiplicaiton */
+/* Auxiliary function for performing GF multiplication */
 val xt2 : bits(8) -> bits(8)
 function xt2(x) = {
   (x << 1) ^ (if bit_to_bool(x[7]) then 0x1b else 0x00)

src/smctr.adoc

@@ -292,7 +292,7 @@ See <<State Enable Access Control>> for cases where CTR accesses from S-mode and
 
 The `ctrsource` register contains the source program counter, which is the `pc` of the recorded control transfer instruction, or the epc of the recorded trap.  The valid (V) bit is set by the hardware when a transfer is recorded in the selected CTR buffer entry, and implies that data in `ctrsource`, `ctrtarget`, and `ctrdata` is valid for this entry.
 
-`ctrsource` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding.  When XLEN < MXLEN, both explicit writes (by software) and implict writes (for recorded transfers) will be zero-extended.
+`ctrsource` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding.  When XLEN < MXLEN, both explicit writes (by software) and implicit writes (for recorded transfers) will be zero-extended.
 
 .Control Transfer Record Source Register Format for MXLEN=64
 [%unbreakable]
@@ -318,7 +318,7 @@ when the recorded transfer is an instruction whose target or
 taken/not-taken direction was mispredicted by the branch predictor. MISP
 is read-only 0 when not implemented.
 
-`ctrtarget` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding.  When XLEN < MXLEN, both explicit writes (by software) and implict writes (by recorded transfers) will be zero-extended.
+`ctrtarget` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding.  When XLEN < MXLEN, both explicit writes (by software) and implicit writes (by recorded transfers) will be zero-extended.
 
 .Control Transfer Record Target Register Format for MXLEN=64
 [%unbreakable]

src/smepmp.adoc

@@ -42,7 +42,7 @@ Without being able to protect less-privileged modes from Machine mode, it is not
 Note that this feature is intended to be used as a debug mechanism, or as a temporary workaround during the boot process for simplifying software, and optimizing the allocation of memory and PMP rules. Using this functionality under normal operation, after the boot process is completed, should be avoided since it weakens the protection of _M-mode-only_ rules. Vendors who don’t need this functionality may hardwire this field to 0.
 ====
 
-. On ``mseccfg`` we introduce a field in bit 1 called *Machine-Mode alloWlist Policy (mseccfg.MMWP)*. This is a sticky bit, meaning that once set it cannot be unset until a *PMP reset*. When set it changes the default PMP policy for M-mode when accessing memory regions that don’t have a matching PMP rule, to *denied* instead of *ignored*.
+. On ``mseccfg`` we introduce a field in bit 1 called *Machine-Mode Allowlist Policy (mseccfg.MMWP)*. This is a sticky bit, meaning that once set it cannot be unset until a *PMP reset*. When set it changes the default PMP policy for M-mode when accessing memory regions that don’t have a matching PMP rule, to *denied* instead of *ignored*.
 
 . On ``mseccfg`` we introduce a field in bit 0 called *Machine Mode Lockdown (mseccfg.MML)*. This is a sticky bit, meaning that once set it cannot be unset until a *PMP reset*. When ``mseccfg.MML`` is set the system's behavior changes in the following way:
 
@@ -113,7 +113,7 @@ Also when ``mseccfg.MML`` is set, according to 4b it’s not possible to add a _
 +
 [WARNING]
 ====
-*Be aware that RLB introduces a security vulnerability if left set after the boot process is over and in general it should be used with caution, even when used temporarily.* Having editable PMP rules in M-mode gives a false sense of security since it only takes a few malicious instructions to lift any PMP restrictions this way. It doesn’t make sense to have a security control in place and leave it unprotected. Rule Locking Bypass is only meant as a way to optimize the allocation of PMP rules, catch errors durring debugging, and allow the bootrom/firmware to register executable _Shared-Region_ rules. If developers / vendors have no use for such functionality, they should never set ``mseccfg.RLB`` and if possible hard-wire it to 0. In any case *RLB should be disabled and locked as soon as possible*.
+*Be aware that RLB introduces a security vulnerability if left set after the boot process is over and in general it should be used with caution, even when used temporarily.* Having editable PMP rules in M-mode gives a false sense of security since it only takes a few malicious instructions to lift any PMP restrictions this way. It doesn’t make sense to have a security control in place and leave it unprotected. Rule Locking Bypass is only meant as a way to optimize the allocation of PMP rules, catch errors during debugging, and allow the bootrom/firmware to register executable _Shared-Region_ rules. If developers / vendors have no use for such functionality, they should never set ``mseccfg.RLB`` and if possible hard-wire it to 0. In any case *RLB should be disabled and locked as soon as possible*.
 ====
 +
 [NOTE]

src/vector-crypto.adoc

@@ -922,7 +922,7 @@ This extension is shorthand for the following set of other extensions:
 [NOTE]
 ====
 This extension combines the NIST Algorithm Suite with the
-GCM/GMAC extension to enable high-performace AES-GCM.
+GCM/GMAC extension to enable high-performance AES-GCM.
 ====
 
 <<<
@@ -997,7 +997,7 @@ This extension is shorthand for the following set of other extensions:
 [NOTE]
 ====
 This extension combines the ShangMi Algorithm Suite with the
-GCM/GMAC extension to enable high-performace SM4-GCM.
+GCM/GMAC extension to enable high-performance SM4-GCM.
 ====
 
 <<<
@@ -4570,7 +4570,7 @@ is recommended reading in order to best understand the supporting code.
 
 [source,sail]
 ----
-/* Auxiliary function for performing GF multiplicaiton */
+/* Auxiliary function for performing GF multiplication */
 val xt2 : bits(8) -> bits(8)
 function xt2(x) = {
   (x << 1) ^ (if bit_to_bool(x[7]) then 0x1b else 0x00)
@@ -4588,13 +4588,13 @@ function gfmul( x, y) = {
   (if bit_to_bool(y[3]) then xt2(xt2(xt2(x))) else 0x00)
 }
 
-/* 8-bit to 32-bit partial AES Mix Colum - forwards */
+/* 8-bit to 32-bit partial AES Mix Column - forwards */
 val aes_mixcolumn_byte_fwd : bits(8) -> bits(32)
 function aes_mixcolumn_byte_fwd(so) = {
   gfmul(so, 0x3) @ so @ so @ gfmul(so, 0x2)
 }
 
-/* 8-bit to 32-bit partial AES Mix Colum - inverse*/
+/* 8-bit to 32-bit partial AES Mix Column - inverse*/
 val aes_mixcolumn_byte_inv : bits(8) -> bits(32)
 function aes_mixcolumn_byte_inv(so) = {
   gfmul(so, 0xb) @ gfmul(so, 0xd) @ gfmul(so, 0x9) @ gfmul(so, 0xe)