SCB.ICSR.VECTACTIVE is 9 bits, not 8
#373
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r? @therealprof (rust-highfive has picked a reviewer for you, use r? to override) |
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added
S-waiting-on-review
src/peripheral/scb.rs
Outdated
| @@ -300,7 +301,7 @@ impl VectActive { | |||
| 12 => VectActive::Exception(Exception::DebugMonitor), | |||
| 14 => VectActive::Exception(Exception::PendSV), | |||
| 15 => VectActive::Exception(Exception::SysTick), | |||
| irqn if irqn >= 16 => VectActive::Interrupt { irqn }, | |||
| irqn if irqn >= 16 && irqn < 512 => VectActive::Interrupt { irqn: irqn - 16 }, | |||
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the - 16 was added to be consistent with how vect_active does it
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Is that a breaking change?
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Yes, but I think the rest of this PR is too
| @@ -170,9 +170,10 @@ impl SCB { | |||
| /// Returns the active exception number | |||
| #[inline] | |||
| pub fn vect_active() -> VectActive { | |||
| let icsr = unsafe { ptr::read(&(*SCB::ptr()).icsr as *const _ as *const u32) }; | |||
| let icsr = | |||
| unsafe { ptr::read_volatile(&(*SCB::ptr()).icsr as *const _ as *const u32) } & 0x1FF; | |||
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changed to read_volatile like cortex-m-rt did to prevent optimizations here
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rebased on top of the asm PR to fix CI |
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Thanks! I think we can merge this now that master is explicitly for 0.8 development, but could you add a changelog entry, especially highlighting the |
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whoops, sure! I also added an entry for my change in #367 since I forgot that too. |
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Build succeeded! And happy new year! 🎉 |
Closes #332